Solid-State Devices TRIZ Cases

Clock-free dataflow logic fabric uses asynchronous blocks and interconnects to raise operating speed while staying compatible with EDA tools.

A mirrored interconnect layout shortens critical FPGA routing paths, reducing wiring delay while preserving flexible logic block connectivity.

Internal positive feedback and current-mirror loads create hysteresis in a Hall sensor comparator while cutting die size and power use.

By turning control gates horizontal and channels vertical, MaCS eases 3D NAND processing and cuts substrate contact resistance.

A buffer layer and fixed charge storage layer shift oxide TFT threshold voltage positive, reduce leakage current, and protect the gate insulator.

Segmented and tree-based priority encoder circuits cut ripple-delay paths and avoid oscillating loops for high-speed operation.

A drain-side Schottky electrode lets a monolithic HEMT or MESFET handle reverse voltage without depletion-region cutoff or a discrete diode.

Colossal magnetocapacitive gate materials store charge in the transistor channel to retain memory data without continuous power.

Selective power-off switches shut down unused LUT memory groups to cut leakage current and dynamic power in FPGA logic circuits.

Dynamic switching links analog, digital, and I/O blocks inside a PSoC to expand peripheral flexibility while reducing power and silicon area.

Series diodes create an internal body tie bias that lowers CMOS threshold voltage, cuts parasitic capacitance, and reduces power use.

Embedded SGLNVM cells replace SRAM LUT storage to retain FPGA configuration after power-off while cutting initialization time and power.

Fine-grain pipeline registers and multiplexers shorten long PLD routing paths to sustain high-speed signal transfer across larger dies.

A shared polysilicon control path aligns latch-array logic devices to improve transistor matching, area use, and SoC block performance.

Storage elements embedded in configurable routing fabric hold signals for arbitrary durations, cutting delay and unnecessary toggling in ICs.

Bidirectional routing tracks and distribution spines let clock roots move within the chip to cut skew, delay, and hold timing issues.

A staged PCIe DMA data link loads bulk configuration data faster than a traditional port, cutting programmable IC setup time.

SAFE and dormant FPGA configurations switch operating modes and sanitize memory on tamper detection to hinder copying and reverse engineering.

Time-domain FPGA FIR filtering mitigates optical dispersion with lower cost and complexity than traditional frequency-domain equalization.

Short vertical routing segments and row multiplexers let a spare logic row repair defects with less wiring overhead and better yield.

Shared-select multiplexers handle shift, gating, and signal selection in FPGAs, freeing logic elements and routing for user designs.

Using paired resistive non-volatile memory cells, this CLB preserves LUT data through power loss while cutting SRAM power and SoC integration cost.

A two-stage output and interconnect selection scheme cuts routing area and crosstalk by sharing drivers across programmable interconnect types.

Unused FPGA bus lines are forced into high impedance to cut parasitic multiplexer leakage and lower standby power in static states.

Selective power-down of unused PLD logic blocks and routing regions cuts leakage current and lowers static and total power use.

Selective memory frame updates use decompression, decryption, and error checking to cut full-chip reconfiguration overhead.

Co-located multiplexers and acknowledge circuitry cut routing overhead and delay in self-timed PLD fanout paths.

Power-on-reset gating lets one analog multiplexer accept signals from different supply domains without forward-bias errors or test sequencing overhead.

Shared configuration memory controls multiple programmable switches to cut circuit area while preserving reconfigurable interconnect flexibility.

Built-in nonvolatile configuration memory enables real-time logic reconfiguration without external memory, improving speed while reducing module size and cost.

Embedded storage in configurable routing fabric reduces signal delay and supports simultaneous signal routing and storage in ICs.

Precomputed delay timing lets a PCB synchronize control signals across unequal lead lengths, simplifying layout and improving space use.

Real-time software access lets configurable logic cells change logic paths on the fly, cutting extra resources and power use.

Dynamic inductor switching lets a resonant clock grid span wider frequencies, cut global clock power, and keep waveforms stable.

Distributed transparent and clocked storage in IC routing fabric holds signals without fixed clock edges, reducing delay and preserving logic flow.

Parallel polarity detection and amplitude comparison give Hall switches omnipolar response without multi-step delay, cutting die area and power.

A solid electrolyte switching layer controls ion-driven current paths to cut leakage and improve scalable RRAM array operation.

A variable resistance element stores multi-bit signals as memorized resistance states, cutting latch count, circuit size, and power use.

Clockless dataflow logic fabric removes synchronous waiting delays, enabling faster circuit operation while staying compatible with existing EDA tools.

A die expansion bus links original and supplemental chip bus subsystems to add resources with low redesign effort, stable pinout, and separate clock domains.

Selective signal registration in a programmable interconnect shortens long routing delays while limiting area and delay overhead.

Cascade multiplexers and controlled output drivers let programmable logic regions share one interconnect bus without simultaneous drive conflicts.

Single-metal-layer conductor rerouting adapts on-chip interface buffers to different dedicated device I/O needs while cutting redesign cost and delay.

Automated netlist tracing links PLD tile select pins to configuration memory outputs, cutting manual model errors and update time.

Programmable switch detection disables unused macrocell clock buffers in PLDs, cutting unnecessary toggling and power draw.

Floating-gate transistors merge switching and memory in large-scale FPAAs, enabling compact reconfigurable analog processing and rapid prototyping.

A base-template IC layout with controlled connector regions cuts unique pattern counts, enabling SMO convergence without sacrificing density.

A programmable 24-bit SPI address register lets one PROM hold and load multiple FPGA configurations from different start addresses.

Unipolar metal-oxide switches cut cross-point latch set-reset cycles, improving latching speed, stability, and manufacturability.

Mask-programmable or configurable interface buffers adapt on-chip I/O between logic and dedicated blocks without full circuit redesign.