Macrocell Clock Buffer Gating for Lower-Power PLDs
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Solution Overview
Problem
Programmable logic devices (PLDs) such as CPLDs and FPGAs consume higher power due to unnecessary clock signal buffering, especially as clock speeds increase, leading to reduced battery life in mobile devices.
Innovation Solution
A method that detects programmable switch values in each macrocell to generate a clock control signal, disabling buffers when clock signals are not needed, thereby preventing unnecessary toggling and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If buffers are used to maintain higher frequency clock speeds along clock paths, then clock signal quality is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the buffer system adaptable and adjustable rather than static. Clock buffers are dynamically enabled or disabled based on real-time detection of clock signal requirements in macrocells. The system transitions from a fixed buffer configuration to a dynamic one where buffers are activated only when clock signals are actually needed, reducing unnecessary power consumption while maintaining clock speed quality when required.
Solution Approach 2:
The patent changes the operational state parameter of clock buffers from always-on to conditionally-on based on detected clock signal requirements. By monitoring whether clock signals are present in macrocells and adjusting the buffer enable/disable state accordingly, the system optimizes the balance between clock signal quality and power consumption through parameter changes in buffer operation.
2Reliability
If clock buffers are always enabled to maintain signal quality, then clock signal integrity is improved, but unnecessary power consumption occurs when clock signals are not needed
Solution Approach 1:
The patent implements feedback by detecting the presence or absence of clock signals in macrocells and using this information to control the enable/disable state of clock buffers. The detection mechanism provides feedback about actual clock signal requirements, which then feeds back to the buffer control logic to adjust buffer operation accordingly, ensuring buffers are active only when needed for maintaining signal integrity.
Solution Approach 2:
The system performs self-service by automatically detecting its own clock signal requirements and autonomously controlling buffer enable/disable states without external intervention. The clock buffer control mechanism serves itself by monitoring the actual need for clock buffering and adjusting its own operational state to match requirements, eliminating unnecessary power consumption while maintaining signal integrity when needed.
3Productivity
If high clock rates are used to increase processing power, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent applies segmentation by dividing the clock buffer control into individual macrocell-level decisions rather than a unified system-wide approach. Each macrocell independently detects its own clock signal requirements and controls its associated buffers separately. This segmentation allows high clock rates to be maintained in macrocells that need processing power while disabling buffers in macrocells that don't require clocking, thus maintaining productivity where needed while reducing overall power consumption.
Data Source
AI summary
An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable switch values in each macrocell and generating a clock control signal based on the switch values. The clock control signal controls a macrocell buffer used for compensating for distortion of clock signals inputted to the macrocell. The macrocell buffer is disabled if the clock signals are not being used by the corresponding macrocell, thereby preventing unnecessary toggling and power consumption.