Programmable Priority Encoder Circuits With Reduced Logic Depth
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Solution Overview
Problem
Conventional programmable priority encoders face challenges with long timing paths and infinite delays at high clock speeds due to ripple carry implementation and closed combinational loops, making them inefficient for high-speed operations.
Innovation Solution
The implementation of low-depth programmable priority encoders and circular programmable priority encoders using efficient circuit designs that reduce propagation delay and Boolean logic gate count, employing techniques such as segmentation, scanning processes, and quaternary logic to reorganize calculations into trees, thereby reducing depth without increasing gate count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ripple carry implementation is used in conventional programmable priority encoders, then the circuit structure is simple and easy to implement, but the timing path becomes long causing 2N-3 Boolean gate delay and limiting operation at high clock speeds
Solution Approach 1:
The encoder circuit is divided into multiple parallel segments or blocks, each handling a portion of the priority encoding independently. This segmentation breaks the long sequential ripple carry path into shorter parallel paths, reducing the critical timing path and enabling higher clock speeds while maintaining the essential encoding functionality.
Solution Approach 2:
The design transitions from a one-dimensional sequential ripple carry structure to a multi-dimensional parallel architecture. By organizing the encoding logic across multiple dimensions (parallel blocks, hierarchical levels), the circuit achieves shorter propagation delays without sacrificing implementation simplicity.
2Device complexity
If conventional ripple carry implementation is used, then the circuit design is straightforward, but the Boolean gate count and propagation delay increase significantly
Solution Approach 1:
The encoding function is segmented into multiple independent or semi-independent blocks that operate in parallel. Each block processes a subset of inputs and generates intermediate results, which are then combined. This segmentation reduces the critical path delay while keeping individual block designs simple and manageable.
Solution Approach 2:
Multiple parallel encoding paths are merged at intermediate stages to produce the final encoded output. By combining results from parallel paths rather than sequentially propagating through all inputs, the circuit achieves lower propagation delay while maintaining a relatively simple overall structure.
3Adaptability or versatility
If circular programmable priority encoder with closed combinational loop is used, then the encoder can handle circular priority scenarios, but the loop can oscillate causing effectively infinite delay
Solution Approach 1:
The problematic oscillating feedback loop is extracted or broken from the combinational logic path. By removing the closed loop that causes oscillation while preserving the essential circular priority encoding functionality through alternative logic structures, the circuit achieves reliable operation without infinite delays.
Solution Approach 2:
An intermediary mechanism or logic element is introduced to mediate the circular priority determination without creating a direct combinational loop. This intermediary breaks the oscillation path while still enabling the encoder to correctly handle circular priority scenarios where the highest priority request wraps around to the beginning.
Data Source
AI summary
An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.