Relay Electrode Interconnection for TFT Signal Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional liquid crystal display devices face issues with high aperture rate and high definition due to the formation of L-shaped grooves during the etching process, leading to improper processing and potential short-circuiting between signal and drain electrodes, especially when the pitch of signal lines is reduced below 20 μm, making it difficult to maintain a high aperture rate and definition.
Innovation Solution
The proposed solution involves a TFT array substrate structure with relay electrodes that connect signal lines to the drain or source electrodes via a layer different from the signal line formation, eliminating concave areas and preventing etchant retention, thus preventing improper processing and allowing for a higher aperture rate and definition by maintaining the integrity of the signal line width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pitch of signal lines is reduced below 20 μm to achieve high definition, then the definition is improved, but L-shaped grooves are formed during etching causing improper processing and potential short-circuiting
Solution Approach 1:
The patent introduces a relay electrode layer positioned at a different height dimension (on the insulating film layer) to connect signal lines to drain electrodes. This vertical dimensionality change eliminates the L-shaped groove problem by avoiding lateral connections at the same etching plane, thus preventing etchant retention while maintaining high definition with reduced pitch signal lines.
Solution Approach 2:
The relay electrode acts as an intermediary component between the signal line and drain electrode. Instead of directly connecting them (which creates L-shaped grooves), the relay electrode mediates the connection through a different layer, eliminating the harmful groove structure while enabling proper electrical connection.
2Productivity
If the pitch of signal lines is reduced below 20 μm to achieve high aperture rate, then the aperture rate is improved, but the space between adjacent signal lines becomes insufficient for proper electrode arrangement
Solution Approach 1:
By moving the connection structure to a different vertical dimension (using the relay electrode on the insulating film layer), the patent enables high aperture rate with reduced pitch signal lines while maintaining proper electrode arrangement. The vertical separation allows compact lateral spacing without compromising the ability to properly arrange and connect electrodes.
3Reliability
If L-shaped grooves are formed during etching to connect signal lines and drain electrodes, then the connection is achieved, but etchant retention occurs causing improper processing and short-circuiting
Solution Approach 1:
The relay electrode serves as an intermediary that eliminates the L-shaped groove structure entirely. By connecting signal lines to drain electrodes through this intermediate element on a different layer, the patent achieves reliable electrical connection without creating the geometric configuration that causes etchant retention, thus ensuring both connection reliability and processing quality.
Solution Approach 2:
The patent extracts and removes the harmful L-shaped groove structure from the design by using a vertical connection approach through the relay electrode. This extraction of the problematic geometric feature eliminates the root cause of etchant retention while preserving the essential electrical connection function.
Data Source
AI summary
A liquid crystal display device achieving high aperture rate and high definition is disclosed. The liquid crystal display device comprises a plurality of scanning lines 12, an insulating film 21 covering the plurality of scanning lines, a plurality of signal lines 13 having an intersection 13D with each of the scanning lines 12, pixel electrodes formed adjacent to the scanning line and the signal line, a plurality of thin film transistors, each of which having a gate electrode, drain electrode 14b, and source electrode 14a, a gate electrode connected to a semiconductor layer, a gate insulating film, and the scanning lines, a drain electrode 14b or a source electrode 14a connected to the signal lines, the other of the drain and the source electrodes connected to the pixel electrode, the drain electrode and the source electrode are linearly disposed along the signal lines, and a plurality of relay electrodes 17 in which a first overlapped portion 17a overlaps the intersection 13D and a second overlapped portion 17c overlaps one of the electrodes, thus connecting that electrode to the signal lines. The first overlapped portion of the relay electrode has a length sufficient to cover the stepped portions 13E, 13D of the insulating film 21 corresponding to the both ends 12b, 12c of the scanning line 12 in a width direction.