Memory Device Select FET Threshold Voltage Shift Recovery
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Solution Overview
Problem
Conventional memory devices face challenges in achieving high integration and efficient operation of resistance change elements, particularly in maintaining the reliability of select FETs due to threshold voltage shifts and hot carrier generation, which affects data retention and storage performance.
Innovation Solution
A memory device configuration incorporating resistance change elements connected between conductive lines, a semiconductor layer, and a select FET with a control circuit that adjusts threshold voltage shifts by setting specific potentials for conductive lines and gate electrodes, and executing recovering operations to neutralize trapped carriers, thereby enhancing data retention and storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If resistance change elements are highly integrated in memory device, then storage capacity and integration density are improved, but threshold voltage shifts and hot carrier trapping in select FETs worsen, reducing reliability
Solution Approach 1:
The patent applies preliminary action by performing a recovering operation before normal read/write operations to neutralize hot carriers and adjust threshold voltage in advance. This preventive measure ensures select FETs start in an optimal state, preventing reliability degradation from occurring in the first place during high-density integration operations
Solution Approach 2:
The patent implements periodic action by repeatedly applying recovering operations at regular intervals during memory device operation. This periodic recovery process continuously neutralizes accumulated hot carriers and corrects threshold voltage shifts, maintaining select FET reliability over extended periods of high integration density operation
2Productivity
If write/erase operations are performed frequently on resistance change elements, then data storage capability is improved, but hot carrier trapping in select FETs increases, causing threshold voltage shifts and reducing operation reliability
Solution Approach 1:
The patent applies continuity of useful action by seamlessly integrating recovering operations into the normal operation cycle without interrupting data processing workflows. The control circuit automatically inserts recovering operations at appropriate intervals, ensuring continuous maintenance of select FET reliability while maintaining high data write/erase productivity
Solution Approach 2:
The patent implements self-service by enabling the memory device to automatically perform recovering operations through its control circuit without requiring external intervention. The system monitors its own operational state and autonomously applies threshold voltage adjustment and hot carrier neutralization, allowing the device to self-maintain reliability during frequent write/erase operations
3Speed
If high current is applied to resistance change elements for fast switching, then operation speed is improved, but hot carrier generation in select FETs increases, leading to threshold voltage shifts and reduced device lifespan
Solution Approach 1:
The patent converts the harmful effect of hot carrier generation into a beneficial process by utilizing the recovering operation to deliberately induce controlled hot carrier flow in the opposite direction. This intentional hot carrier injection during recovery neutralizes previously trapped carriers and restores threshold voltage, transforming the harmful hot carrier phenomenon into a self-correcting mechanism that extends select FET operational lifespan despite high-speed switching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables high integration and reliable operation of memory devices by reducing threshold voltage shifts and hot carrier effects, improving data retention and storage efficiency while maintaining high performance and reducing erroneous writing/erasing.
Implementation Method 1
a resistance change element (56) functioning as a memory cell MC... it transitions between at least two resistance values: a low resistance state (LRS) and a high resistance state (HRS)... a bipolar operation element, in which a transition from a high resistance state to a low resistance state and a transition from a low resistance state to a high resistance state are performed by application of voltages with different polarities
Implementation Method 2
a channel region (6)... a select gate line (8)... a select element (SS)... a select FET using the semiconductor layer as a channel
Implementation Method 3
hot carriers are easily trapped in the gate oxide film, and it is likely that a long-term characteristic variation such as a reduction of an ON current and/or an increase of an OFF current will become remarkable... a variation in a characteristic of the select element (SS) (for example, threshold value shift)
Implementation Method 4
impact-ionized hot carriers are generated by an electric field at the drain terminal... electrons generated by this are attracted to the gate electrode having a large voltage
Data Source
AI summary
According to one embodiment, a memory device includes a semiconductor layer connected between a first conductive line and one end of a third conductive line, resistance change elements connected between second conductive lines and the third conductive line respectively, a select FET having a select gate electrode, and using the semiconductor layer as a channel, and a control circuit executing a write/erase of at least one of the resistance change elements, and executing a recovering operation which adjusts a threshold voltage shift of the select FET after the write/erase.