Programmable Interconnect Layout for Self-Timed Acknowledge Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional programmable logic devices (PLDs) face challenges in implementing self-timed circuit environments due to the difficulty in asserting a main acknowledgement signal when data is fanned out to multiple destinations, which leads to delays and increased resource consumption in configuration memory and routing resources.
Innovation Solution
The implementation of a programmable interconnect network with co-located configuration memory cells, multiplexers, and acknowledge circuitry in an interconnect block, which reduces metal usage and facilitates efficient layout for self-timed circuit applications by allowing multiplexers to control both fanout and acknowledge signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is fanned out to multiple destinations using conventional forking, then routing flexibility is improved, but acknowledgement signal assertion becomes difficult and delays increase
Solution Approach 1:
The patent combines the data fanout path and acknowledgement signal path through the use of multiplexers. The same multiplexer that routes data to multiple destinations is also used to route the acknowledgement signal back to the sender, merging two previously separate functions into a single integrated structure. This resolves the contradiction by allowing flexible routing while maintaining a clear, unified acknowledgement path.
Solution Approach 2:
The multiplexer is designed to perform multiple functions: it acts as a data router during data transmission and as an acknowledgement router during acknowledgement transmission. This multi-functionality eliminates the need for separate dedicated acknowledgement routing resources, thereby reducing delays while preserving routing flexibility.
2Reliability
If separate acknowledge routing resources are provided for each fanout destination, then acknowledgement reliability is improved, but configuration memory and routing resources increase
Solution Approach 1:
The patent merges the data routing function and acknowledgement routing function into a single multiplexer structure. Instead of providing separate dedicated acknowledge routing resources for each fanout destination, the same multiplexer resources are reused for both purposes. This significantly reduces configuration memory requirements and routing resource complexity while maintaining reliable acknowledgement delivery.
Solution Approach 2:
The multiplexer is designed as a universal routing element that can dynamically switch between data transmission mode and acknowledgement transmission mode. This multi-functionality allows a single set of routing resources to handle both data and acknowledgements reliably, eliminating the need for duplicate dedicated resources and thereby reducing device complexity.
3Ease of manufacture
If conventional interconnect networks are used, then implementation simplicity is maintained, but suitability for self-timed asynchronous circuits decreases
Solution Approach 1:
The patent introduces dynamic control signals that allow the multiplexer to switch between data transmission and acknowledgement transmission modes based on the timing and state of asynchronous events. This dynamic behavior enables the interconnect network to adapt to self-timed asynchronous operation while maintaining a relatively simple structural implementation.
Solution Approach 2:
The patent implements a feedback mechanism where the acknowledgement signal travels back through the multiplexer to the sender, providing real-time feedback about data reception status. This feedback loop is essential for self-timed asynchronous circuits to coordinate data transmission without external clock synchronization, thereby improving suitability for asynchronous operation while keeping the implementation straightforward.
Data Source
AI summary
In an apparatus, an interconnect block includes a plurality of configuration memory cells. A plurality of multiplexers is respectively coupled to the configuration memory cells. An acknowledge circuit is coupled to the configuration memory cells. The acknowledge circuit includes a plurality of acknowledge inputs. The configuration memory cells are coupled to selectively set states of the plurality of multiplexers and correspondingly selectively activate inputs of the plurality of acknowledge inputs. A data ready circuit is coupled to at least one multiplexer output of the plurality of multiplexers.