NAND Memory Cell Initialization via Fringe Induced Barrier Lowering
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Solution Overview
Problem
NAND memory cells face inefficiencies in programming and erasing operations, particularly in 2-bits/cell applications, due to the second bit effect, which affects the overall performance and reliability of the memory cell array.
Innovation Solution
The proposed solution involves initializing a NAND memory cell by creating an operation environment with a fringe induced barrier lowering (FIBL) effect, achieved by injecting carriers into carrier storage elements positioned along the edges of isolation structures, thereby turning on specific channel regions and enhancing the programming and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional programming and erasing operations are used in NAND memory cells, then the memory cell can perform basic storage functions, but the second bit effect reduces operation efficiency and reliability
Solution Approach 1:
The patent applies preliminary action by initializing the NAND memory cell before programming operations. The initialization process applies a positive bias between the gate and substrate to inject carriers into the carrier storage element along the edges of isolation structures, creating an optimized starting state that eliminates the second bit effect and improves subsequent programming efficiency
Solution Approach 2:
The patent applies local quality by creating non-uniform carrier distribution within the carrier storage element. Carriers are specifically injected and accumulated along the edges of isolation structures rather than uniformly throughout, creating localized high-concentration regions that generate the fringe induced barrier lowering effect to improve operation reliability
2Reliability
If carriers are uniformly distributed in the carrier storage element, then the memory cell maintains simple structure, but the fringe induced barrier lowering effect is insufficient
Solution Approach 1:
The patent creates localized carrier accumulation regions along the edges of isolation structures within the carrier storage element. This non-uniform distribution generates the necessary fringe induced barrier lowering effect while maintaining the physical simplicity of the device structure, as no additional components are required
Solution Approach 2:
The isolation structures serve as intermediaries that guide and concentrate carrier injection. By applying positive bias, carriers are injected from the gate and naturally accumulate along the isolation structure edges, using the isolation structures themselves as mediators to achieve the desired carrier distribution pattern
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the efficiency of NAND memory cell operations and reduces the second bit effect, improving the program and erase efficiency while expanding the operation window, as demonstrated by the reduced second bit effect and enhanced performance in 2-bits/cell structures.
Implementation Method 1
applying a positive bias between the gate and the substrate of the NAND memory cell so that a plurality of carriers are injected into the carrier storage element above the edges of the isolation structures
Implementation Method 2
programming and erasing operations are via +Vg F-N (Fowler-Nordheim) and −Vg FN tunneling effect
Implementation Method 3
The 2-bits/cell operation is performed with CHE (channel-hot-electron) program and +Vg FN erase methods
Data Source
AI summary
The invention is directed to a NAND memory cell at an initializing state. The NAND memory cell at the initializing state comprises a substrate, a gate, at least two doped regions, a carrier storage element and a plurality of carriers. The substrate has at least two isolation structures formed therein and the isolation structures are parallel to each other. The gate is disposed over the substrate and across the isolation structures. The doped regions are disposed at both sides of the gate in the substrate between the isolation structures respectively. The carrier storage element is disposed between the substrate and the gate. The carriers are disposed in the carrier storage elements and aggregating above the edges of the isolation structures.