Split Gate NVM and Logic Transistor Integration via Dummy Gate Replacement
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Solution Overview
Problem
There is a need to enhance the performance of integrated circuits that combine non-volatile memory (NVM) and logic functions without sacrificing logic performance or increasing costs, particularly in the context of the gate last technique, where high-performance gates and dielectrics are required while maintaining cost efficiency.
Innovation Solution
The integration of a split gate non-volatile memory cell with a select gate and control gate, where the select gate is connected to the word line over a recessed isolation region, allowing for chemical mechanical polishing (CMP) to access a dummy gate in the logic region, and subsequent replacement with a metal gate, enabling efficient strapping to the silicided select gate, while maintaining high performance and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate last technique is used to enhance logic performance with high-performance gates and dielectrics, then logic performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the fabrication process into distinct regions: NVM regions where polysilicon gates are retained, and logic regions where dummy gates are removed and replaced with metal gates. This segmentation allows different gate structures to coexist on the same chip, enabling high-performance logic while maintaining NVM functionality without requiring complete process overhaul.
Solution Approach 2:
The patent implements preliminary actions by forming dummy gates over high-k gate dielectric early in the fabrication process, before final gate material decisions are made. These dummy gates serve as placeholders that can be selectively removed in logic regions while being retained in NVM regions, streamlining the overall manufacturing process.
2Reliability
If dummy gates are replaced with metal gates in logic regions, then conductance and dielectric properties are improved, but additional process steps increase cost
Solution Approach 1:
The patent applies local quality by implementing metal gates only in logic regions where high performance is required, while retaining polysilicon gates in NVM regions. This selective approach optimizes conductance and dielectric properties where needed without incurring the full cost of metal gate implementation across the entire chip.
Solution Approach 2:
The dummy gate structure serves multiple functions: it acts as a placeholder during fabrication, defines the gate region geometry, and can be selectively removed or retained based on the desired device type. This multi-functionality reduces the need for additional specialized structures and process steps.
3Reliability
If high-k dielectric is used with metal gates, then dielectric constant is increased for better performance, but process integration becomes more difficult
Solution Approach 1:
The high-k gate dielectric is formed early in the fabrication process, before final gate material deposition. This preliminary formation allows the high-k dielectric to serve as a foundation for both metal gates in logic regions and polysilicon gates in NVM regions, simplifying subsequent processing steps.
Solution Approach 2:
The patent utilizes parameter changes in the gate dielectric layer, specifically employing high-k materials with different dielectric constants to optimize device performance. By controlling the dielectric constant parameter, the patent achieves better electrical characteristics while maintaining compatibility with standard fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient integration of logic and NVM cells using a gate last process, achieving high performance and cost-effectiveness by enabling the replacement of dummy gates with metal gates, thereby improving conductance and dielectric properties without increasing costs.
Implementation Method 1
A subsequent step of chemical mechanical polishing (CMP) is able to provide access to a dummy gate in a logic region of the integrated circuit
Data Source
AI summary
A method of making a split gate non-volatile memory (NVM) using a substrate includes etching a recess into an isolation region of an NVM region of the substrate and depositing a conductive layer and a capping layer. A select gate and a control gate are formed in the NVM region, and a dummy gate is formed in a logic region of the substrate. A portion of the capping layer is removed and a salicide block bi-layer is deposited and patterned to form a first opening that exposes a contact portion of the conductive layer over the recess. A silicided region is formed on the contact portion. The substrate is planarized to expose the dummy gate, which is replaced with a metal gate. A second opening is etched through a first interlayer dielectric deposited over the substrate to the silicided region. Contact metal is deposited into the second opening.