Pipelined Direct-Drive Routing With Fine-Grain Signal Delay Control
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Solution Overview
Problem
As the die size of programmable logic devices (PLDs) increases, existing routing architectures face challenges in supporting high-speed data transmission across the die efficiently, particularly in optimizing logic density and signal routability between logic elements.
Innovation Solution
The implementation of a pipelined direct-drive routing architecture that incorporates a routing multiplexer, flip-flop, and mode multiplexer, or a pulse latch, to delay and manage signals effectively, allowing for efficient high-speed data transmission by pipelining at a fine grain level, including individual logic elements and routing wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the die size of PLDs is increased to support more logic elements and routing channels, then the logic density and signal routability are improved, but the signal transmission delay and routing complexity increase
Solution Approach 1:
The patent introduces pipeline registers that segment the routing path into multiple stages, allowing signals to be transmitted through different segments at different clock cycles. This segmentation breaks down long transmission paths into manageable segments, reducing the overall transmission delay across large die sizes while maintaining high signal transmission speed.
Solution Approach 2:
The patent employs anticipatory routing techniques where routing decisions are made in advance at earlier stages of the signal path. By pre-configuring routing paths and making forwarding decisions before signals reach critical bottlenecks, the system reduces signal delay and improves transmission efficiency across expanded die sizes.
2Adaptability or versatility
If more routing channels and logic elements are added to increase logic density, then the device functionality is improved, but the routing architecture complexity increases
Solution Approach 1:
The routing architecture is segmented into standardized stages with uniform pipeline registers and routing multiplexers. This modular segmentation allows the system to scale logic density by repeating standardized units rather than designing complex custom routing paths, thereby reducing architectural complexity while increasing adaptability.
Solution Approach 2:
The patent implements universal pipeline registers and routing multiplexers that can handle multiple signal types and routing configurations. These universal components serve multiple functions across different routing contexts, reducing the need for specialized complex routing logic and enabling high logic density with manageable architectural complexity.
3Productivity
If pipelining is implemented at fine grain level to improve signal transmission speed, then the productivity is improved, but the device complexity increases
Solution Approach 1:
The patent merges the functionality of pipeline registers with routing multiplexers into integrated units. By combining these functions, the system achieves fine-grain pipelining for high data transmission efficiency while reducing the overall device complexity through functional integration rather than separate components.
Solution Approach 2:
The pipeline registers are designed as universal components that can be shared across multiple routing paths and logic elements. This multi-functionality allows fine-grain pipelining to be implemented efficiently without requiring dedicated pipeline registers for each routing path, thereby improving data transmission efficiency while controlling the complexity of the register pool.
Data Source
AI summary
One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.