RRAM Memory Cells With Deep Trench Isolation For Lithography Accuracy
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Solution Overview
Problem
Conventional memory structures face challenges in improving performance due to the shrinking lithography process window for forming well regions in semiconductor devices, which affects the accuracy and size of memory cells.
Innovation Solution
The proposed solution involves forming memory cells with a substrate that includes consecutively arranged diode regions, different doping types in well regions, and a deep trench isolation structure to electrically isolate these regions, along with an RRAM device connected to the doped conductive regions, thereby increasing the lithography process window and improving position accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the lithography process window is reduced to improve memory cell miniaturization, then the area size of memory cells decreases, but the position accuracy of well regions deteriorates
Solution Approach 1:
The substrate is divided into multiple diode regions (first, second, third, and fourth diode regions) arranged consecutively in a row direction. By segmenting the well region formation into separate diode regions with deep trench isolation structures between them, each region can be independently controlled and positioned, thereby maintaining position accuracy even as the overall memory cell area is reduced.
Solution Approach 2:
Deep trench isolation structures are introduced as intermediary elements between adjacent diode regions. These isolation structures serve as physical and electrical barriers that define the boundaries of each well region, enabling precise positioning and electrical isolation. The deep trench isolation structures act as mediators that allow miniaturization while preserving manufacturing precision through clear spatial demarcation.
2Reliability
If deep trench isolation structures are added to improve electrical isolation, then manufacturing complexity increases, but device performance improves
Solution Approach 1:
The deep trench isolation structures serve multiple functions simultaneously: they provide electrical isolation between adjacent diode regions, define the boundaries for well region formation, and act as physical barriers to prevent dopant diffusion. By merging these multiple functions into a single structural element, the fabrication process complexity is minimized while achieving reliable electrical isolation and precise positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of memory cells by increasing the lithography process window, improving position accuracy, and reducing the area size of memory cells, aligning with the miniaturization trend in semiconductor development.
Implementation Method 1
a deep trench isolation structure formed in the substrate. The deep trench isolation structure electrically isolates the first well region in the first diode region from the first well region in the second diode region, the second well region in the third diode region from the second well region in the fourth diode region, the doped conductive region in the first diode region from the doped conductive region in the second diode region, and the doped conductive region in the third diode region from the doped conductive region in the fourth diode region
Implementation Method 2
The RRAM is a nonvolatile memory developed based on the electrically-induced-resistance-change effect of some materials. The material of the insulation layer in the MIM capacitor has the electrically-induced-resistance-change property. That is, the resistance of the material used to form the insulation layer in the MIM capacitor can be reversibly changed under the control of specific external signals.
Implementation Method 3
two diodes (D) with rectification characteristics are integrated in each RRAM (R) device to form a 2D1R memory array structure. When the 2D1R memory array structure is applied to a memory structure, the memory structure may demonstrate advantages of high operation current and low leakage current.
Implementation Method 4
forming a first well region in the substrate of the first diode region and the second diode region, and a second well region formed in the substrate in the third diode region and the fourth diode region. The doping type of the second well region is different from the doping type in the first well region.
Data Source
AI summary
A memory cell includes a substrate including a first diode region, a second diode region, a third diode region, and a fourth diode region, a first well region formed in the first diode region and the second diode region, a second well region formed in the third diode region and the fourth diode region, a doped conductive region formed on the first well region and the second well region, and a deep trench isolation structure formed in the substrate to electrically isolate different portions of each of the first well region, the second well region, and the doped conductive region formed over different diode regions. The second well region and the first well region have different doping types. The memory cell includes a resistance random access memory device formed over the substrate and electrically connected to the doped conductive region in the second diode region and the third diode region.