Columnar Gate Electrodes for Self-Aligned Channel Formation
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Solution Overview
Problem
Conventional FINFET structures face challenges in miniaturization due to increased parasitic resistance and alignment errors during gate patterning, limiting the ability to achieve high performance and further miniaturization.
Innovation Solution
The semiconductor device features plural columnar gate electrodes formed in a row on a semiconductor substrate, with a gate sidewall film filling the space between adjacent electrodes to create a self-aligned channel region, reducing parasitic resistance and alignment errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the FIN width is reduced for miniaturization, then the device size is reduced, but the parasitic resistance of source and drain regions increases
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional columnar gate structure that extends vertically into the substrate. This dimensional change allows the gate to wrap around and control the channel from multiple directions, improving gate control efficiency and reducing parasitic resistance in the source and drain regions while maintaining miniaturization benefits
2Manufacturing precision
If an alignment margin is incorporated in the FIN pattern to account for lithography alignment errors, then manufacturing robustness is improved, but the FIN length must be longer than the gate width
Solution Approach 1:
The columnar gate structure is formed using a self-aligned process where the gate pattern defines its own position relative to the source and drain regions. The gate sidewall film is formed conformally on the gate structure, automatically creating the precise spacing needed without requiring additional alignment steps or margins, thus eliminating the F>L+G constraint
3Ease of manufacture
If the gate electrode is formed after forming the SOI region in the FIN shape, then the manufacturing process is simplified, but alignment errors occur during gate patterning
Solution Approach 1:
The patent forms the gate pattern first, then uses this pre-formed gate structure as a template to define the source and drain region positions. The gate sidewall film is formed conformally on the gate structure before etching, ensuring that the source and drain regions are automatically aligned to the gate with precise spacing, eliminating alignment errors
Data Source
AI summary
A semiconductor device has plural columnar gate electrodes for plural MOSFETs formed in a row separately on a semiconductor substrate, and a semiconductor region which is formed in a part between the neighboring two columnar gate electrodes of the plural columnar gate electrodes to form a channel of the MOSFETs.