Thin Film Transistor Substrate Asymmetric Drain Electrode Misalignment Compensation
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Solution Overview
Problem
Mask misalignment during the production of thin film transistor substrates leads to variations in drain-to-gate parasitic capacitance, causing uneven response to gate pulsing signals and undesirable visual artifacts in liquid crystal displays.
Innovation Solution
A thin film transistor substrate design where the drain electrode is formed to be longer than the gate electrode, ensuring a constant overlap area even with misalignment, and is positioned perpendicular to the gate line to maintain consistent parasitic capacitance and kickback voltage across the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate electrode and drain electrode are formed with standard overlapping dimensions, then the manufacturing process is simple and fast, but mask misalignment causes variations in parasitic capacitance leading to uneven pixel response
Solution Approach 1:
The drain electrode is designed with an asymmetric structure where its length in the longitudinal direction exceeds the gate electrode's length, creating an intentional overlap extension. This asymmetric design ensures that even with mask misalignment, the overlapping area between gate and drain electrodes remains consistent, thereby maintaining uniform parasitic capacitance across all pixels without requiring complex manufacturing processes
Solution Approach 2:
The electrode structure is pre-designed with built-in compensation features before manufacturing. The drain electrode's extended length and perpendicular orientation are predetermined in the design stage to automatically compensate for potential mask misalignment during production, eliminating the need for post-manufacturing adjustments or complex alignment procedures
2Manufacturing precision
If the drain electrode is made longer to compensate for misalignment, then parasitic capacitance consistency is improved, but the electrode area and material usage increase
Solution Approach 1:
The asymmetric electrode design extends the drain electrode only in the necessary direction (longitudinal direction beyond gate electrode length) while maintaining standard dimensions in other directions. This targeted extension provides the required overlap for capacitance consistency without unnecessarily increasing the total electrode area or material consumption across the entire substrate
3Manufacturing precision
If the drain electrode is positioned perpendicular to the gate line, then misalignment compensation is maximized, but the electrode layout complexity increases
Solution Approach 1:
The perpendicular positioning of the drain electrode relative to the gate line creates an asymmetric overlap configuration that maximizes misalignment compensation. This orientation ensures that the overlapping area remains stable regardless of mask shifts, and the simple perpendicular relationship actually simplifies the layout rules compared to more complex angular arrangements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design maintains consistent image quality across the panel by keeping parasitic capacitance and kickback voltage constant, preventing flicker and ensuring optimal common voltage values, even with mask misalignment.
Implementation Method 1
This overlap corresponds to a drain-to-gate parasitic capacitance that is sometimes referred to as a Miller capacitance
Data Source
AI summary
A thin film transistors (TFTs) substrate is structured to maintain as constant across the area of the substrate a kickback voltage due to Miller capacitance between the drain and gate of each TFT even in the presence of manufacturing induced misalignments between the drain electrodes and corresponding gate lines. Each thin film transistor includes a gate electrode, an active layer formed on the gate electrode so as to overlap the gate electrode, first and second source electrodes respectively connected to first and second data lines each of which crosses the gate line while being insulated from the gate line, and an elongated drain electrode located between the first and second source electrodes and disposed over the gate electrode so as to a crossing length of the drain electrode is larger than an underlying width of the gate electrode such that misalignment induced shifts of the position of the gate electrode relative to the drain electrode does not substantially change overlap area between the two.