Mirrored FPGA Interconnect Layout for Shorter Wiring Delays
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Solution Overview
Problem
There is a need to improve programmable integrated circuits to increase the types of user designs that can be implemented, particularly by reducing wiring delays and enhancing performance through optimized interconnect structures.
Innovation Solution
The implementation of a programmable integrated circuit with a mirrored interconnect structure, featuring horizontally arranged logic and interconnect columns, where programmable interconnect blocks are vertically arranged and coupled to logic blocks to minimize wiring delays and improve performance by utilizing predominantly shorter connections for critical timing paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional interconnect structure is used in programmable logic devices, then the device can be manufactured with standard architecture, but wiring delays increase and performance deteriorates due to longer connection paths
Solution Approach 1:
The patent applies asymmetry by introducing a mirrored interconnect structure where interconnect columns are positioned asymmetrically relative to logic columns. Specifically, interconnect columns are placed adjacent to logic columns in a non-uniform pattern, creating shorter connection paths for critical timing paths while maintaining manufacturability. This asymmetric arrangement reduces wiring delays by optimizing the physical distance between interconnected elements.
Solution Approach 2:
The patent utilizes dimensional optimization by arranging interconnect columns and logic columns in a multi-dimensional grid pattern. The mirrored interconnect structure extends the interconnect architecture into additional spatial dimensions, allowing signals to traverse shorter paths by utilizing vertical and horizontal interconnect layers strategically. This dimensional approach enables shorter single connections without increasing overall device complexity.
2Productivity
If longer interconnect paths are used to connect logic blocks, then the interconnect structure can be simpler, but performance decreases due to increased wiring delays
Solution Approach 1:
The patent segments the interconnect structure into multiple distinct interconnect columns, each serving specific logic columns. This segmentation allows for optimized routing where critical timing paths utilize dedicated short-distance interconnect columns, while non-critical paths can use other routes. The segmentation of interconnect resources enables parallel signal paths and reduces the length of critical connections, thereby improving overall device performance.
3Loss of time
If the interconnect structure is optimized for shorter connections, then wiring delays are reduced, but the device complexity increases
Solution Approach 1:
The mirrored interconnect structure implements universality by designing interconnect columns that can serve multiple logic columns simultaneously. Each interconnect column is configured to provide connections to adjacent logic columns in a mirrored pattern, allowing a single interconnect column to fulfill multiple routing functions. This multi-functional design reduces the total number of interconnect columns needed, thereby reducing wiring delays without proportionally increasing device complexity.
Data Source
AI summary
A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interconnect column includes programmable interconnect blocks (148), and each of the first and second logic columns includes programmable logic blocks. Each programmable interconnect block provides a plurality of first input and output ports on a first side and a plurality of second input and output ports on a second side. The first ports and the first side of each of the programmable interconnect blocks physically mirror the second ports and the second side of the programmable interconnect block. The ports of the programmable interconnect blocks are coupled to the ports of the programmable logic blocks in the first and second logic columns.