MIS Transistor Source-Drain Alignment for Hot Carrier Suppression
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Solution Overview
Problem
Conventional NAND-type EEPROMs suffer from program disturbance due to hot carrier generation and performance differences between n-type and p-type MIS transistors, primarily because the direction from the source to the drain in memory cells is aligned with the [110]-direction of the semiconductor substrate, leading to reduced operational reliability and current driving performance.
Innovation Solution
The direction from the source to the drain in each MIS transistor is aligned parallel to the [001]- or [010]-direction of the semiconductor substrate, which suppresses hot carrier injection and improves the performance of both n-type and p-type MIS transistors, thereby enhancing the operational reliability and current driving capability of NAND-type EEPROMs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the direction from source to drain in memory cells is aligned with the [110]-direction of the semiconductor substrate, then it facilitates placement of transistors and resist openings in photolithography steps, but it causes program disturbance due to hot carrier generation and creates performance differences between n-type and p-type MIS transistors
Solution Approach 1:
The patent changes the crystal orientation parameter of the semiconductor substrate from the conventional [110]-direction to the [001]-direction for the source-to-drain alignment in memory cells. This parameter change fundamentally alters the carrier transport characteristics, suppressing hot carrier generation while maintaining manufacturing feasibility, thereby resolving the contradiction between ease of manufacture and operational reliability
2Device complexity
If carriers in MIS transistors flow in the [110]-direction of the semiconductor substrate, then the conventional structure is maintained, but the performance of n-type MIS transistors becomes larger than that of p-type MIS transistors, creating a performance difference
Solution Approach 1:
The patent changes the crystal orientation parameter from [110] to [001] for carrier flow direction in MIS transistors. This parameter change equalizes the mobility characteristics of both n-type and p-type transistors by utilizing the symmetric properties of the [001] direction in silicon crystal, thereby achieving consistent performance across different transistor types while maintaining structural simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This alignment significantly prolongs the lifetime of hot carrier injection, reduces program disturbance, and improves the current driving performance of p-type MIS transistors, leading to improved operational reliability and reduced chip size, as the performance difference between n-type and p-type transistors is minimized.
Implementation Method 1
a charge storage layer formed on a (001)-plane of a semiconductor substrate with a gate insulating film interposed therebetween and configured to store data
Implementation Method 2
a gate insulating film interposed therebetween
Data Source
AI summary
A semiconductor memory device includes a memory cell block. The memory cell block includes a plurality of n-type first MIS transistors with current passages connected in series. Each of the first MIS transistors includes a source, a drain, and a charge storage layer formed on a (001)-plane of a semiconductor substrate with a gate insulating film interposed therebetween and is configured to store data. A direction from the source to the drain in each of the first MIS transistors is set parallel to a [001]-direction or [010]-direction of the semiconductor substrate.