MaCS Nonvolatile Memory Layout for Easier 3D NAND Scaling
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Solution Overview
Problem
Conventional three-dimensional NAND flash memories face challenges in increasing memory capacity due to difficulties in processing control gates and high contact resistance between the semiconductor substrate and active areas, particularly in BiCS-NAND structures.
Innovation Solution
A new architectural concept, MaCS (Matrix Channel Stacked memory), replaces semiconductor layers and control gates in the BiCS-NAND structure, allowing control gates to pass through semiconductor layers horizontally and eliminating the need for a line & space pattern, thereby reducing contact resistance and enabling easier scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers is increased to increase memory capacity, then storage capacity is improved, but processing of control gates formed across the stacked layer structure becomes difficult
Solution Approach 1:
Instead of forming control gates across stacked layers (conventional approach), this patent inverts the approach by stacking control gates horizontally and forming active areas vertically through holes. This inversion simplifies the processing by eliminating the need to form gates across multiple stacked layers, thereby resolving the manufacturing difficulty while maintaining increased storage capacity through vertical stacking of memory cells.
Solution Approach 2:
The patent transitions from a conventional three-dimensional structure where control gates are stacked vertically to a new architecture where control gates are stacked horizontally (in the first direction), while active areas extend vertically (in the second direction). This dimensional reorganization allows for simplified processing of control gates while achieving high density through vertical stacking of memory cells in the third direction.
2Quantity of substance
If BiCS-NAND structure is used to extend NAND series vertically, then memory capacity is increased, but contact resistance between semiconductor substrate and active area becomes great
Solution Approach 1:
The patent inverts the conventional BiCS-NAND structure by placing control gates horizontally and forming active areas vertically through holes in the gate stack. This inversion allows the active area to make direct contact with the semiconductor substrate at the bottom, eliminating the high contact resistance issue in BiCS-NAND where the active area is suspended and requires contact through the gate structure.
3Quantity of substance
If control gates are processed into line & space pattern across stacked layers, then memory density is increased, but processing complexity increases significantly
Solution Approach 1:
Instead of forming control gates in a line-and-space pattern across stacked layers (which requires complex multi-step processing), the patent inverts the approach by forming simple horizontal control gate lines and then creating vertical active areas through the gate stack. This dramatically simplifies the processing while achieving high memory density through the vertical stacking of multiple memory cells sharing common control gates.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.