Semiconductor Storage Device Electrode Segmentation
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Solution Overview
Problem
The existing phase change memory technology faces challenges in configuring electrode wiring lines to efficiently handle different current values for reset, set, and read operations, leading to increased voltage drops and energy consumption due to parasitic capacitance, which affects performance and throughput.
Innovation Solution
The semiconductor storage device employs a configuration where electrode wiring lines are connected via transistors to form large electrodes, allowing for independent operation during read and parallel access to multiple memory cells, while connecting for reset and set operations to reduce resistance and voltage drops, and separating transistors to prevent charge/discharge of parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If electrode wiring lines are made wide to handle large current during reset operation, then current capacity is improved, but parasitic capacitance increases affecting read operation
Solution Approach 1:
The wiring is segmented into multiple narrower lines that can be connected in parallel via transistors. This provides the current capacity of a wide wiring during reset operation while maintaining the lower parasitic capacitance of narrower individual lines during read operation when segments are isolated.
2Reliability
If transistors are used to connect electrode wiring lines, then resistance is reduced for reset operation, but charge/discharge of parasitic capacitance occurs increasing energy consumption
Solution Approach 1:
The transistors are dynamically controlled to be ON during reset operation to enable parallel connection and reduce resistance for adequate drive current. During read operation, transistors are OFF to isolate segments and prevent parasitic capacitance charge/discharge, thus minimizing energy consumption.
3Productivity
If current is flowed to multiple memory cells simultaneously for set operation, then throughput is improved, but voltage drop increases due to cumulative current
Solution Approach 1:
The electrode wiring is segmented and can be connected in parallel via transistors during set operation. This parallel connection reduces the overall resistance, allowing higher cumulative current to flow to multiple memory cells simultaneously without excessive voltage drop, thus maintaining high throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances read/write/erase performance, reduces energy consumption, and improves throughput by minimizing voltage drops and parasitic capacitance effects, resulting in a high-density, low-cost, and high-performance memory array.
Implementation Method 1
data is rewritten by changing an electrical resistance of a phase change film to a different state by a Joule heat generated by the current
Implementation Method 2
The phase change memory stores information using that a resistance value of a phase change material such as Ge2Sb2Te5 is different in an amorphous state and a crystalline state
Implementation Method 3
electrode wiring lines are connected via transistors to form large electrodes, allowing for independent operation during read and parallel access to multiple memory cells, while connecting for reset and set operations to reduce resistance and voltage drops
Data Source
AI summary
In a semiconductor storage device that is formed on a semiconductor substrate, flows a current to a recording material formed between electrodes to change a resistance value of the recording material and store information, and flows currents of different magnitudes in a high resistance change operation and a low resistance change operation, electrodes of a plurality of memory cells are electrically connected directly or via transistors to form large electrodes, the large electrodes are connected to a feeding terminal from a power source circuit, and the large electrodes are connected to large electrodes connected to a feeding terminal from a power source connected between a plurality of memory cells different from the plurality of memory cells via inter-large electrode connection transistors. By using the semiconductor storage device, a connection pattern of a feeding electrode for the memory cells can be configured according to the magnitude of a consumption current, power consumption by a voltage drop by a parasitic resistance of the feeding electrode and power consumption by charge/discharge of a parasitic capacitance around the feeding electrode can be suppressed, and performance per consumption power in read/set/reset operations can be improved.