Asynchronous Reconfigurable Logic Fabric for Clock-Free High-Speed Operation

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Solution Overview

Problem

Conventional reconfigurable logic fabrics are limited by synchronous circuits, which restrict their operational speed and compatibility with existing electronic design automation (EDA) tools.

Innovation Solution

The development of asynchronous reconfigurable logic fabrics that operate independently of clock signals, utilizing dataflow operations represented by 'tokens' and implemented using asynchronous logic blocks, memory blocks, and interconnect elements to enable faster and more flexible logical operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If synchronous circuits are used in reconfigurable logic fabrics, then compatibility with existing EDA tools is maintained, but operational speed is limited due to sequential clock cycle dependencies

Engineering Contradiction:

Improveoperational speedVSAvoidcompatibility with EDA tools

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent inverts the conventional synchronous approach by implementing asynchronous logic circuits that do not rely on clock signals. Instead of using sequential clock cycles to coordinate operations, the invention uses handshaking protocols and event-driven mechanisms where circuits operate independently and communicate through signal transitions, thereby achieving higher speeds while maintaining EDA tool compatibility through abstraction layers

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent introduces intermediary components such as buffer circuits, delay elements, and translation layers that mediate between the asynchronous fabric and synchronous interfaces. These intermediaries enable the asynchronous logic to operate at higher speeds while presenting a synchronous interface to EDA tools, thus resolving the contradiction between speed and tool compatibility

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If sequential arrangements of synchronous circuits are used, then design simplicity is maintained, but computational speed is limited by clock cycle waiting delays

Engineering Contradiction:

Improvecomputational speedVSAvoidcircuit architecture complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments the logic fabric into independent, modular logic elements that can operate autonomously without sequential dependencies. Each logic element is self-contained with its own buffering and control mechanisms, allowing parallel execution of operations across multiple segments, thereby increasing computational speed while managing complexity through modularity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic reconfiguration capabilities where the logic fabric can change its operational characteristics in real-time. Asynchronous circuits allow dynamic adjustment of signal propagation delays and routing paths based on actual data flow conditions, enabling the system to adapt to varying computational requirements without being constrained by fixed clock cycles

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8125242B2Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics

Publication Date: 2012.02.28 ACHRONIX SEMICONDUCTOR CORP

AI summary

In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.