Self-Modifying FPGA Configuration for Anti-Tamper Protection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing electronic systems, particularly those using FPGAs, face challenges in preventing tampering and protecting secure configuration data, as copying or replication of configuration data can compromise sensitive information, leading to loss of intellectual property and security breaches.

Innovation Solution

A self-modifying FPGA system that includes a configuration memory with both SAFE and dormant data, where the FPGA can switch between safe and secure operating modes by loading configuration data from either PROM or SRAM, using configuration assist circuitry to control data loading and sanitize memory upon tampering detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If configuration data is stored in PROM for FPGA, then the FPGA can be programmed in the field, but the configuration data can be copied or replicated leading to security breaches

Engineering Contradiction:
Improvefield programmabilityVSAvoidtampering and copying
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The configuration data is segmented into multiple separate PROMs, each containing only a portion of the total configuration data. The FPGA requires all segments to be present simultaneously to function properly. This segmentation prevents unauthorized copying because obtaining complete configuration data requires access to multiple distributed PROMs rather than a single copyable source.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system implements a hierarchical configuration structure where multiple levels of configuration data are nested. The FPGA first loads initial configuration from one PROM, then uses that configuration to access and load additional configuration segments from other PROMs. This nested approach creates multiple access layers that must all be compromised to fully replicate the system.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Object-affected harmful factors

If multiple configuration PROMs are used to prevent copying, then security is improved, but the device complexity increases

Engineering Contradiction:
Improveanti-tampering capabilityVSAvoidmultiple configuration PROMs
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

Multiple PROMs are designed with identical physical interfaces and data formats, allowing them to be universally interchangeable in the configuration loading process. The FPGA's configuration logic is designed to handle multiple PROMs through a standardized interface, reducing the complexity impact by making the system modular and consistent rather than requiring specialized handling for each PROM.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Object-affected harmful factors

If configuration data is distributed across multiple PROMs, then copying becomes difficult, but the ease of operation decreases

Engineering Contradiction:
Improvecopying preventionVSAvoidconfiguration loading
Core Design Contradiction:
Object-affected harmful factorsVSEase of operation

Solution Approach 1:

The system performs preliminary configuration validation by checking the presence and integrity of all required PROM segments before attempting to load configuration data. This preliminary action prevents operational errors by ensuring all necessary components are available, and the system can gracefully handle missing or invalid PROMs without requiring complex error recovery procedures during normal operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8896346B1Self-modifying FPGA for anti-tamper applications
Publication Date: 2014.11.25 MERCURY SISTEMS INC
  • US8896346B1 patent drawing
  • US8896346B1 patent drawing
  • US8896346B1 patent drawing

AI summary

A self-modifying FPGA system includes an FPGA and a configuration memory coupled to the FPGA for providing the FPGA with configuration data including SAFE configuration data and dormant configuration data. The SAFE configuration data is initially loaded to the FPGA and the FPGA is configured to a safe operating mode. Upon a determination to proceed to a next step of self modification, dormant configuration data contained in the configuration memory is loaded into the FPGA and the FPGA is configured to a secure operating mode.