PLD Tile Controlling Pin Mapping From Netlist Characterization
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Solution Overview
Problem
The manual generation of models for programmable logic devices (PLDs) is time-consuming, prone to errors, and delayed by circuit changes, due to the complexity of tracing signal connections between numerous circuits with similar names.
Innovation Solution
A processor-implemented method determines controlling pins for tile modules in PLD designs by inputting a netlist and characterization data for sub-modules and configuration memory cells, specifying select input pins and data output pins, to automatically generate configuration data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual model extraction is performed by inspection of schematics and tracing signal connections, then model accuracy can be achieved, but the process becomes time-consuming and error-prone due to the numerous circuits and similar names
Solution Approach 1:
The patent replaces the manual mechanical process of tracing signal connections through schematics with an automated computer-based system. The system uses a netlist data structure and algorithmic processing to automatically trace connections and generate models, eliminating the need for manual inspection and tracing while maintaining accuracy.
Solution Approach 2:
The patent creates a digital representation (copy) of the PLD circuitry through netlists and data structures that mirror the actual circuit connections. This digital model can be processed automatically without requiring physical inspection of schematics, enabling rapid model generation while preserving accuracy.
2Productivity
If manual model extraction is performed by inspection of schematics, then models can be generated, but the process is prone to errors due to the complexity and similarity of circuit names
Solution Approach 1:
The patent replaces manual model extraction with an automated computer-based system that processes netlists and traces connections algorithmically. This eliminates human errors associated with manual inspection of complex schematics with similar circuit names, significantly improving reliability while maintaining productivity.
Solution Approach 2:
The system incorporates verification mechanisms that trace signal connections through the netlist and validate the generated models against the original circuit description. This feedback process ensures accuracy and detects errors automatically, reducing the error rate compared to manual methods.
3Adaptability or versatility
If circuit changes are made late in PLD development, then design flexibility is improved, but model availability is delayed by the time-consuming manual extraction process
Solution Approach 1:
The patent creates a dynamic model generation system that can automatically update models when circuit changes occur. The automated process using netlists and algorithms can rapidly regenerate models in response to design modifications, enabling late-stage circuit changes without significant delays in model availability.
Solution Approach 2:
The system establishes a automated model generation framework in advance that can quickly adapt to circuit changes. By having the infrastructure ready, the system can rapidly regenerate models when design changes occur late in development, minimizing the time penalty associated with adaptability.
Data Source
AI summary
A processor-implemented method is provided for determining controlling pins of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of a tile module are input. Characterization data is input for a sub-module of the tile module that specifies a select input pin controlling a programmable function of the sub-module, which is either a multiplexer or a logic site. Characterization data is input for a configuration memory cell of the tile module that specifies a data output pin of the configuration memory cell. The controlling pin is determined for each select input pin of each instance of the sub-module of the tile module. The controlling pin of a select input pin is the data output pin of an instance of a configuration memory cell of the tile module. A specification is output of the select input pin and corresponding controlling pin.