IC Layout Regions Using Controlled Patterns for SMO Printability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Advanced IC processes (e.g., 22 nm and below) face challenges in reliably printing arbitrary geometric patterns due to complex interactions between neighboring features, with existing techniques failing to achieve effective source-mask optimization (SMO) without significant sacrifices in layout density.
Innovation Solution
The approach involves defining an underlying regular construct (baseTemplate) and allowing specific deviations (connectorTemplates) to create circuit components, reducing the number of unique neighborhood patterns and enabling deterministic SMO by using a limited set of base and connector templates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional layout techniques (RDR, gridded, etc.) are used to reduce pattern complexity, then the number of neighborhood patterns is reduced, but layout density is significantly sacrificed
Solution Approach 1:
The layout is segmented into a regular repeating base fabric and controlled deviation regions. The base fabric provides a consistent pattern framework that reduces overall pattern complexity, while localized deviations allow circuit components to be formed without significantly increasing the number of unique neighborhood patterns. This segmentation enables maintaining high layout density while controlling pattern complexity.
Solution Approach 2:
Instead of applying uniform pattern restrictions across the entire layout, the invention applies deviations locally at specific positions where circuit components are needed. The base fabric maintains regularity in most regions, while localized deviations create the necessary circuit functionality. This local quality approach minimizes the number of unique patterns while preserving layout density in the majority of the design area.
2Manufacturing precision
If source-mask optimization (SMO) is applied to advanced IC processes, then printability is improved, but computational burden increases significantly
Solution Approach 1:
The invention performs preliminary action by establishing a regular base fabric with predetermined patterns before applying SMO. This pre-structuring reduces the complexity of the optimization problem, allowing SMO to converge more quickly and with lower computational burden. The base fabric provides a stable foundation that guides the optimization process rather than requiring SMO to solve the entire layout from scratch.
Solution Approach 2:
The invention changes the parameter space by constraining layouts to use only a limited set of base templates and connector templates. This parameter reduction transforms the optimization problem into a more manageable form that requires less computational resources while still achieving effective SMO convergence for advanced IC processes.
3Adaptability or versatility
If arbitrary geometric patterns are printed in advanced IC processes, then design flexibility is maintained, but printing reliability deteriorates
Solution Approach 1:
The invention maintains design flexibility through local deviations from the base fabric while ensuring printing reliability through the regularity of the base pattern itself. The base fabric uses patterns that are known to print reliably in advanced processes, while localized deviations introduce the necessary design variety. This approach ensures that the majority of the layout consists of reliable, proven patterns while still allowing design flexibility where needed.
Solution Approach 2:
The invention uses a homogeneous base fabric with repeating patterns that print reliably in advanced IC processes. This homogeneity ensures consistent printing behavior across most of the layout. Controlled deviations are applied locally to introduce design variety while maintaining overall pattern consistency, thus preserving printing reliability while achieving necessary design flexibility.
Data Source
AI summary
The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization.