FPGA SPI Multi-Boot State Machine With Programmable PROM Addressing

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Solution Overview

Problem

Conventional FPGAs do not utilize the available 24-bit address functionality of SPI PROMs, limiting them to loading configurations starting from an address of all zeros, which restricts the ability to store and retrieve multiple configurations from a single SPI PROM.

Innovation Solution

Incorporating a programmable SPI address register into the SPI state machine of the FPGA, allowing for a 24-bit programmable start address to be sent with a read command, enabling multiple configurations to be loaded from a single SPI PROM by using the 24-bit address to specify different starting points for configuration data within the PROM.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional FPGA uses fixed address loading from SPI PROM, then the configuration loading process is simple, but the ability to store and retrieve multiple configurations from a single SPI PROM is restricted

Engineering Contradiction:

Improveability to store and retrieve multiple configurationsVSAvoidconfiguration loading process complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a programmable address register that can be dynamically loaded with different 24-bit addresses, allowing the FPGA to access different configuration blocks in the SPI PROM. This dynamic address capability enables multiple configurations to be retrieved from a single PROM without requiring multiple fixed-address loading mechanisms, thus improving versatility while maintaining manageable complexity through a single programmable register.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The invention changes the address parameter from a fixed value (all zeros) to a programmable 24-bit value. By allowing the address register to be programmed with different starting addresses, the system can selectively access different configuration data blocks within the SPI PROM, enabling multiple configurations to be stored and retrieved using the same hardware interface.

Inventive Principle:

Principle #35Parameter changes

2Quantity of substance

If FPGA uses only 16-bit address register, then the hardware implementation is simpler, but the addressable range in SPI PROM is limited

Engineering Contradiction:

Improveaddressable configuration data rangeVSAvoidaddress register bit width

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from a 16-bit address space to a 24-bit address space, effectively adding another dimension of addressing capability. This 8-bit expansion provides access to 256MB of addressable space in the SPI PROM, enabling storage of multiple complete FPGA configurations within a single PROM chip, thus dramatically increasing the quantity of storable configurations.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If multiple configurations are stored in separate SPI PROMs, then each configuration can be accessed independently, but the system complexity and cost increase

Engineering Contradiction:

Improveconfiguration selection capabilityVSAvoidnumber of SPI PROM components

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent makes a single SPI PROM multi-functional by enabling it to store multiple configuration blocks that can be selectively accessed through programmable addressing. The same PROM chip can serve multiple configuration purposes, eliminating the need for multiple separate PROM components while maintaining the ability to independently select and load different configurations into the FPGA.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention merges multiple configuration storage functions into a single SPI PROM component. By combining multiple configuration blocks within one PROM and using a programmable address register to select between them, the system consolidates what would traditionally require multiple separate PROM chips into a single integrated solution, reducing component count and system complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS7425843B1Programmable logic device multi-boot state machine for serial peripheral interface (SPI) programmable read only memory (PROM)

Publication Date: 2008.09.16 XILINX INC

AI summary

Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorporated into a SPI state machine of the PLD. A read command followed by a first address corresponding to first configuration data is sent from the SPI address register of the SPI state machine of the PLD to the SPI PROM. Data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address corresponding to second configuration data. The first configuration data is stored in the PLD memory, and the second address is stored in the SPI address register. These steps may be repeated for subsequent boots of the PLD for additional configurations of the PLD.