Non-Volatile LUT Architecture for Fast FPGA Initialization
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Solution Overview
Problem
Conventional Field Programmable Gate Arrays (FPGAs) face challenges with volatile SRAM-based Look-Up-Table (LUT) configurations, leading to lost data upon power off and slow initialization due to the need for separate non-volatile memory units, which are costly and power-consuming, limiting their scalability and performance.
Innovation Solution
The implementation of Single Gate Logic Non-Volatile Memory (SGLNVM) devices within each Logic Element (LE) as Non-Volatile LUT (NV-LUT), using minimal logic gate length for charge storage with embedded control gates, allowing direct digital signal output without sensing amplifiers, enabling faster, more efficient, and scalable non-volatile configuration data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM-based LUTs are used in FPGA, then the device can be configured with volatile memory, but the configuration data is lost after power off and initialization is slow due to separate non-volatile memory units
Solution Approach 1:
The patent merges the non-volatile memory storage function directly into the LUT structure by replacing conventional SRAM cells with SGLNVM cells. This integration eliminates the need for separate non-volatile memory units and their associated sensing circuitry, allowing configuration data to be retained without power while enabling direct digital signal output for faster initialization.
2Reliability
If separate non-volatile memory units are used to store configuration data, then non-volatile storage is achieved, but power consumption increases and circuit complexity increases due to sensing circuitry requirements
Solution Approach 1:
The SGLNVM cells inherently provide digital signal output capability without requiring external sensing amplifiers. The non-volatile memory cells serve their primary storage function while simultaneously providing direct digital outputs that can be used by the LUT logic, eliminating the need for separate sensing circuitry and reducing overall power consumption.
3Reliability
If separate non-volatile memory units with sensing circuitry are used, then non-volatile configuration storage is achieved, but device complexity and cost increase
Solution Approach 1:
The patent combines the non-volatile memory storage function and the digital signal output function into a single integrated SGLNVM cell structure. This merging eliminates the need for separate sensing amplifiers and associated control logic, thereby reducing circuit complexity and manufacturing cost while maintaining non-volatile configuration storage capability.
4Reliability
If conventional NVM devices with sensing amplifiers are used, then non-volatile storage is achieved, but initialization speed decreases due to data fetching and loading processes
Solution Approach 1:
The SGLNVM cells are designed to directly output digital signals that can be immediately used by the LUT logic without requiring data fetching, sensing, or loading processes. This self-service capability eliminates multiple intermediate steps in the initialization sequence, enabling faster system startup while maintaining non-volatile configuration storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides faster initialization, reduced power consumption, and multiple-time configurability, meeting demands for high logic gate counts and performance in configurable digital circuitries without increasing process costs, and enabling direct integration of non-volatile memory within each LE.
Implementation Method 1
The threshold voltages of SGLNVM devices are shifted to a higher voltage state after programmed by injecting electrons to the single floating gate
Implementation Method 2
the threshold voltages of SGLNVM devices can be erased to a low voltage state by removing the electrons from the floating gates
Implementation Method 3
or slightly injecting holes in the floating gates
Data Source
AI summary
Innovative Non-Volatile Look-Up-Table (NV-LUT) has been constructed by Single Gate Logic Non-Volatile Memory (SGLNVM) devices processed with the standard CMOS logic process. One of a pair of complementary SGLNVM devices is always programmed to the high threshold voltage state and the other remains in the low threshold voltage state. By applying digital voltage rail (VDD and VSS) to the input nodes of the pair of complementary SGLNVM devices, the output node of the pair of complementary SGLNVM devices outputs digital signals according to its configuration. The NV-LUT outputs digital signals from a plurality of pairs of complementary SGLNVM devices through a digital switching multiplexer. The NV-LUT is a good substitution for SRAM based LUT commonly used in Field Programmable Gate Array (FPGA).