Shared Interconnect Bus Control for Programmable Logic Regions
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Solution Overview
Problem
Programmable integrated circuits face inefficiencies due to static configuration of interconnects, which leads to unused resources when only a subset of inputs is required, resulting in wasteful use of interconnects and potential conflicts when multiple logic regions try to drive the interconnect bus simultaneously.
Innovation Solution
The integration of multiplexing circuitry in a cascade structure, dynamically controlled by control circuitry, allows only one programmable logic region to drive the interconnect bus at a time, using tristate drivers and bi-directional driver circuitry to manage signal flow and prevent simultaneous driving, thereby optimizing interconnect usage and preventing conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interconnects are statically configured to route data to logic circuits, then routing functionality is provided, but interconnect efficiency deteriorates when only a subset of inputs is required
Solution Approach 1:
The patent implements dynamic interconnect configuration by replacing static routing with time-multiplexed signal switching. Multiplexer circuits dynamically select which logic region outputs are routed to the shared interconnect bus based on current operational requirements, allowing the interconnect structure to adapt its configuration in real-time rather than being fixed during fabrication.
Solution Approach 2:
The shared interconnect bus serves multiple logic regions simultaneously through time-division multiplexing. A single interconnect bus structure is made universal by allowing different logic regions to share it at different time intervals, eliminating the need for dedicated interconnect paths for each logic region and reducing overall interconnect resource requirements.
2Productivity
If multiple programmable logic regions are coupled to a shared interconnect bus, then interconnect resource sharing is achieved, but simultaneous driving conflicts occur
Solution Approach 1:
The patent implements periodic time-division multiplexing where each logic region is granted exclusive access to the shared interconnect bus in alternating time slots. Control circuitry generates periodic enable signals that systematically activate one logic region's output at a time, ensuring rhythmic, conflict-free access patterns that prevent simultaneous driving while maximizing resource utilization.
Solution Approach 2:
The patent introduces multiplexer circuits and control logic as intermediary components between logic regions and the shared interconnect bus. These intermediaries act as mediators that manage access requests, resolve conflicts, and coordinate signal transmission, preventing direct simultaneous driving while maintaining reliable signal integrity through controlled access protocols.
3Adaptability or versatility
If static configuration is used for interconnects, then device simplicity is maintained, but adaptability deteriorates when different input subsets are needed
Solution Approach 1:
The patent changes the operational parameter of interconnect configuration from static to dynamic by introducing time-varying control signals. The multiplexer circuits respond to changing control parameters that indicate which logic region should currently access the interconnect bus, allowing the system to adapt to different operational modes and input requirements by modifying the temporal parameters of signal routing rather than the physical structure.
Data Source
AI summary
An integrated circuit may include programmable logic regions coupled in parallel to an interconnect bus. Multiplexing circuitry may be interposed between the programmable logic regions and the interconnect bus. The multiplexing circuitry may be formed from multiplexing circuits formed in a cascade structure. The multiplexing circuitry may dynamically receive control signals that determines which programmable logic region is allowed to drive output signals onto the interconnect bus. Alternatively, each programmable logic region may have an associated output circuit that is coupled to the interconnect bus. The output circuits may be dynamically controlled by control circuitry. The output circuits may receive control signals from the control circuitry that selectively enable and selectively disable the output circuits. The output circuits may be formed with logic circuitry that ensures that the interconnect bus is not simultaneously driven by the output circuits.