Pipelined Unidirectional Interconnect for Clock Skew Reduction
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Solution Overview
Problem
Designing reliable clock networks for large programmable integrated circuits (ICs) is challenging due to clock skew issues, which require significant engineering resources and can impact the design cycle, and the extensive global clock networks consume substantial power.
Innovation Solution
The integration of pipelined unidirectional programmable interconnect structures with substantially similar logic blocks and routing structures, each including storage elements, and the use of handshake circuits with C-elements to control multi-bit busses, reduces clock skew and eliminates the need for large global clock networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive dedicated global clock networks are used to provide clock signals to all portions of the IC, then clock distribution coverage is improved, but power consumption increases substantially
Solution Approach 1:
The patent extracts the clock signal distribution function from the data path by using dedicated clock management blocks and global clock networks that operate independently from the programmable interconnect structures. This separation allows clock signals to be distributed reliably without consuming power through the same pathways used for data transmission.
Solution Approach 2:
The patent introduces clock management blocks as intermediary components that buffer and manage clock signal distribution. These blocks include features like clock deskewing, frequency synthesis, and phase shifting to ensure reliable clock distribution across the IC without requiring excessive power consumption through the programmable interconnect.
2Reliability
If complex clock management blocks with DLLs, PLLs, and DCMs are implemented to handle clock skew, then clock signal reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the IC into multiple clock management blocks, each serving a specific region or portion of the device. This segmentation allows complex clock management functions to be distributed and localized rather than centralized, reducing the complexity burden on any single block while maintaining overall clock signal reliability across the entire IC.
3Productivity
If pipelined unidirectional programmable interconnect structures are used with storage elements, then throughput is improved, but clock skew issues arise that require additional design resources
Solution Approach 1:
The patent extracts the timing synchronization function from the clock network by using handshake circuits that operate independently of global clock signals. Each logic block and routing structure uses local handshake protocols to ensure proper timing and data validity without relying on skew-sensitive global clock distribution.
Solution Approach 2:
The patent implements handshake circuits with feedback mechanisms that use ready and acknowledge signals to communicate data validity and readiness between logic blocks and routing structures. This feedback-based timing synchronization eliminates the need for complex clock skew management while maintaining reliable operation in pipelined architectures.
4Adaptability or versatility
If global clock networks are designed to reach virtually any position in the IC, then clock accessibility is improved, but design and testing time increases
Solution Approach 1:
The patent segments clock distribution into multiple regional clock management blocks, each providing clock signals to a specific portion of the IC. This segmentation improves clock accessibility to various positions without requiring a single extensive global clock network, thereby reducing design and testing complexity and time.
Data Source
AI summary
Integrated circuits (ICs) having pipelined unidirectional programmable interconnect structures are provided. Substantially similar logic blocks in an IC each include at least one storage element driving an output of the logic block. The IC also includes programmable routing structures, each of which includes at least one storage element unidirectionally driving an output of the routing structure without traversing any pass gates. Each routing structure has at least one unidirectional output that drives another of the routing structures or one of the logic blocks. Each logic block has at least one output that drives an input of a programmable routing structure. The logic blocks and the programmable routing structures may be interconnected by unidirectional data lines organized as multi-bit busses coupled to multi-bit ports of the logic blocks and routing structures. Each routing structure may include a handshake circuit coupled to control all bits in one of the multi-bit busses.