Asynchronous Reconfigurable Logic Fabric for Clockless High-Speed Circuits
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Solution Overview
Problem
Conventional reconfigurable logic fabrics are limited by sequential arrangements of synchronous circuits, which restrict their operational speed and compatibility with existing electronic design automation tools.
Innovation Solution
The development of asynchronous reconfigurable logic fabrics that operate independently of clock signals, utilizing dataflow operations represented as 'tokens' and implemented with asynchronous logic blocks, memory blocks, and interconnect elements to enable faster and more flexible logical operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If synchronous circuits are arranged in sequence within the fabric, then the logic fabric can be configured using conventional EDA tools, but the operational speed is limited due to clock cycle delays
Solution Approach 1:
The patent inverts the conventional synchronous approach by implementing asynchronous logic elements that do not rely on clock signals. Instead of forcing sequential operation through clock cycles, the invention allows logic elements to operate independently and propagate signals asynchronously, thereby achieving higher speeds without the bottleneck of synchronized clocking.
Solution Approach 2:
The patent introduces dynamic configuration capabilities where the logic fabric can be reconfigured after fabrication. This dynamic reconfigurability allows the system to adapt its structure and functionality, enabling complex operations to be performed through parallel asynchronous pathways rather than fixed sequential arrangements.
2Speed
If asynchronous logic elements are used to increase speed, then operational speed improves to 1 GHz clock-equivalent performance, but compatibility with existing EDA design tools becomes problematic
Solution Approach 1:
The patent employs an intermediary translation layer that converts asynchronous logic designs into a form compatible with conventional EDA tools. This intermediary mechanism allows designers to use standard synchronous design flows while the underlying hardware operates asynchronously, bridging the gap between design tool capabilities and hardware performance requirements.
Solution Approach 2:
The patent changes the fundamental timing parameter from synchronous clock cycles to asynchronous event-driven operation. By altering the temporal parameter from fixed clock periods to variable signal propagation delays, the system achieves higher speeds while maintaining design tool compatibility through abstracted representation methods.
3Productivity
If sequential synchronous circuits are used, then design compatibility is maintained, but each circuit must wait for the previous circuit to complete, limiting overall throughput
Solution Approach 1:
The patent implements continuous useful action by eliminating idle waiting periods between logic operations. Asynchronous signal propagation allows downstream circuits to begin processing as soon as their inputs are ready, rather than waiting for clock-synchronized completion of upstream circuits. This continuous operation maximizes computational throughput by keeping all logic elements actively productive.
Solution Approach 2:
The patent enables preliminary action by allowing downstream logic elements to prepare and process data before upstream elements have fully completed their operations. The asynchronous architecture permits out-of-order execution and overlapping operations, where later stages can begin work on current data while earlier stages continue processing, thereby reducing overall latency and increasing throughput.
Data Source
AI summary
In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.