Programmable IC Configuration via PCIe Burst Data Link

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The configuration of programmable integrated circuits (ICs) is hindered by the lengthy time required to retrieve configuration data via traditional configuration ports, especially due to the large number of programmable resources in current ICs.

Innovation Solution

Implementing a Peripheral Component Interconnect Express (PCIe) control circuit and data link to facilitate configuration data transfer in burst mode using direct memory access (DMA) mode, allowing for higher data rates and reduced configuration time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If configuration data is retrieved via traditional configuration port, then configuration is simple and reliable, but configuration time becomes prohibitively long

Engineering Contradiction:
Improveconfiguration reliabilityVSAvoidconfiguration time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The configuration data stream is segmented into multiple parts: a first portion containing control logic for the second configuration port, and a second portion containing the actual configuration data. This segmentation allows the system to bootstrap itself with minimal initial data, then load the remaining configuration data through a faster pathway, thereby reducing overall configuration time while maintaining reliability through structured data organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A second configuration port is introduced as an intermediary pathway between the non-volatile memory and the configuration logic. This second port operates in burst mode to transfer configuration data at higher speeds compared to the traditional first configuration port. The intermediary port acts as a bridge that enables faster data transfer while the control logic ensures proper configuration sequencing, thus resolving the contradiction between speed and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If entire configuration data stream is loaded via configuration port, then complete configuration is achieved, but data transfer rate becomes too slow for practical applications

Engineering Contradiction:
Improveconfiguration completenessVSAvoidconfiguration speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The system performs preliminary action by loading a first portion of configuration data containing control logic into the configuration logic through the first configuration port before attempting to load the main configuration data stream. This preliminary configuration enables the system to activate the second configuration port and establish high-speed data transfer capabilities before the bulk configuration data is transferred, thus ensuring both completeness and speed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The configuration process is divided into periodic phases: first, the control logic is loaded and executed to enable the second configuration port; second, the main configuration data stream is transferred in burst mode through the second port; and third, the configuration is finalized. This periodic action allows the system to switch between different data transfer modes optimally, achieving both completeness and high productivity.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8917111B1Configuration of programmable integrated circuits
Publication Date: 2014.12.23 XILINX INC
  • US8917111B1 patent drawing
  • US8917111B1 patent drawing
  • US8917111B1 patent drawing

AI summary

Approaches for configuring programmable resources of a programmable IC are disclosed. A first set of configuration data is loaded using a configuration port of the programmable IC, which also includes input/output (I/O) ports. Programmable resources are configured according to the first set of configuration data to implement a master data link circuit and at least one slave data link circuit. The master data link circuit includes a hardwired communication circuit, and a set of the programmable resources arranged to form a communication control circuit configured to control the communication circuit to provide a data link for communicating data via one of the I/O ports. A second set of configuration data is loaded using the master data link circuit. Programmable resources of the programmable IC are configured according to the second set of configuration data to implement a logic circuit configured to communicate data via the slave data link circuit.