Patterned Substrate for Group III Nitride Growth

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Solution Overview

Problem

Existing semiconductor technologies face challenges in minimizing dislocation density in semiconductor layers, particularly for deep ultraviolet light emitting diodes (DUV LEDs), which affects the efficiency of these devices.

Innovation Solution

A patterned substrate with a substantially flat top surface and stress-reducing openings is used to grow group III-nitride semiconductor layers with high aluminum concentration, where the root mean square roughness of the surface is less than 0.5 nanometers and the openings have a characteristic size between 0.1 microns and 5 microns, allowing for the growth of a layer with a thickness at least twice the size of the openings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional planar substrate growth is used, then the growth process is simple, but dislocation density in the semiconductor layers is high

Engineering Contradiction:
Improvedislocation densityVSAvoidsubstrate structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The substrate surface is segmented into multiple regions with different heights (terraces), creating a stepped structure. This segmentation allows dislocations to be confined to specific regions while maintaining low dislocation density in the active growth areas, thereby improving layer quality without excessive complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a two-dimensional planar substrate to a three-dimensional stepped substrate structure. By introducing vertical dimensionality through controlled terraces and ridges, the substrate provides additional pathways for stress relief and dislocation management, reducing dislocation density in the grown semiconductor layers

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Stress or pressure

If stress-reducing structures are added to the substrate, then stress in semiconductor layers is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvestress in semiconductor layerVSAvoidsubstrate fabrication
Core Design Contradiction:
Stress or pressureVSEase of manufacture

Solution Approach 1:

The stepped structure and stress-reducing features are pre-formed on the substrate before semiconductor layer growth begins. This preliminary action allows the substrate to provide stress relief from the outset of the growth process, reducing stress accumulation in the semiconductor layers without requiring complex post-growth processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The substrate incorporates localized stress-reducing features such as trenches, ridges, and varying terrace geometries at specific locations. These local modifications provide targeted stress management where needed most, while maintaining simpler structures in other areas, thus balancing stress reduction with manufacturing ease

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces dislocation density and stress in the semiconductor layers, enhancing the efficiency and performance of light emitting devices by promoting dislocation-free growth and stress relaxation.

Implementation Method 1

a first layer having a patterned surface, wherein the patterned surface includes a top surface having a root mean square roughness less than approximately 0.5 nanometers and a plurality of openings in the top surface... A layer of group-III nitride material can be grown on the first layer... This approach reduces dislocation density and stress in the semiconductor layers

Methodology Applied
Scientific EffectStress relaxation: Stress Relaxation

Data Source

PatentUS9680061B2Patterned layer design for group III nitride layer growth
Publication Date: 2017.06.13 SENSOR ELECTRONIC TECHNOLOGY INC
  • US9680061B2 patent drawing
  • US9680061B2 patent drawing
  • US9680061B2 patent drawing

AI summary

A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.