Die Expansion Bus for Incremental Chip Resource Upgrades
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Solution Overview
Problem
Existing processing systems face challenges in upgrading performance without substantial redesign, leading to long design cycles and potential delays in meeting market windows due to the need for additional resources not originally designed into the system.
Innovation Solution
The implementation of a die expansion bus that efficiently couples supplemental circuitry to the original processing system, allowing for the integration of additional resources while maintaining the existing design's pinout and minimizing redesign efforts, by providing a low-latency, high-performance bus architecture that extends existing micro-architectural hooks for control and resource access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If substantial chip redesign is performed to meet increased performance demands, then processing system performance is improved, but design cycle time increases and time-to-market is delayed
Solution Approach 1:
The processing system is divided into an original portion and a supplemental portion, each containing bus subsystems that can be independently designed and verified. The die expansion bus couples these separate portions, allowing incremental performance improvement without requiring complete redesign of the entire system.
Solution Approach 2:
The die expansion bus provides a universal interface that couples bus subsystems between the original and supplemental portions, enabling the system to maintain functionality while extending performance capabilities through additional resources.
2Adaptability or versatility
If substantial chip redesign is performed to add additional resources, then processing system capabilities are improved, but verification complexity and cost increase
Solution Approach 1:
The system is segmented into original and supplemental portions with their respective bus subsystems. This segmentation allows verification to be performed separately on each portion and their interconnections, reducing overall verification complexity compared to verifying a completely redesigned system.
Solution Approach 2:
The die expansion bus acts as an intermediary that couples the bus subsystems of the original and supplemental portions. This intermediary structure provides standardized interfaces that simplify verification by establishing clear boundaries and communication protocols between the two portions.
3Adaptability or versatility
If custom portion is coupled to original portion using traditional methods, then additional resources are integrated, but design reuse is limited and pinout changes are required
Solution Approach 1:
The die expansion bus provides a universal coupling mechanism that integrates additional resources while maintaining consistent pinouts. This universal interface enables design reuse by allowing the original portion to remain unchanged while accommodating supplemental portions with similar interface requirements.
Data Source
AI summary
A die expansion bus efficiently couples a supplemental portion of a processing system to an original portion of the processing system on a die. The die expansion bus couples bus subsystems of the supplemental portion of the processing system to the bus subsystems of the original portion of the processing system. The original portion of the processing system is arranged to control the data resources of the supplemental portion of the processing system by accessing memory mapped control registers associated with the bus subsystems of the supplemental portion of the processing system.