Damascene Select Gate Formation in 3D NAND Memory
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Solution Overview
Problem
The existing methods for fabricating three-dimensional vertical NAND devices face challenges in achieving precise dimensional control and efficient formation of select gates, particularly in monolithic arrays, due to the complexity of the process and difficulty in satisfying dual requirements of depth and spacing.
Innovation Solution
A method involving a damascene process is employed to form a conductive select gate electrode by etching a recess in the top insulating layer of a multi-layer stack, depositing a conductive material, and planarizing it to create a select gate adjacent to the semiconductor channel, facilitating improved dimensional control in the three-dimensional NAND-string memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If repeated formation of sidewall spacers and etching of substrate is used to form active regions, then the NAND string structure is achieved, but the process becomes difficult and time consuming with roughly conical active region shape
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming memory openings through the stack, depositing memory films on sidewalls, forming semiconductor channels, and finally creating select gates through damascene process. This segmentation allows each step to be optimized independently, achieving cylindrical active regions without requiring repeated sidewall spacer formation and etching cycles.
Solution Approach 2:
The invention transitions from planar processing to three-dimensional vertical processing by forming memory openings that extend through the entire stack in the vertical dimension. This enables the formation of cylindrical active regions and allows select gates to be positioned at different vertical levels (above and below memory levels), resolving the shape control issue without increasing lateral process complexity.
2Manufacturing precision
If conventional methods are used to form select gates in monolithic arrays, then the NAND string is formed, but precise dimensional control and efficient formation of select gates cannot be achieved
Solution Approach 1:
The damascene process for select gate formation is performed as a preliminary action after channel formation but before final device assembly. The recesses are etched, lined with barrier and conductive materials, and planarized in advance, allowing precise dimensional control of select gates while streamlining the overall fabrication sequence and improving productivity.
Solution Approach 2:
The invention changes the physical and chemical parameters of the fabrication process by using specific deposition techniques for barrier layers and conductive materials, and by controlling etching parameters to create precisely defined recesses. These parameter changes enable accurate control of select gate dimensions and composition without compromising fabrication efficiency.
Data Source
AI summary
A method of fabricating a memory device includes forming a mask over a top surface of a stack of alternating insulating material layers and control gate electrodes located over a substrate, wherein the stack has a memory opening extending vertically through the stack, a semiconductor channel extends vertically in the memory opening, and a memory film is located in the memory opening between the semiconductor channel and the plurality of control gate electrodes, and the mask covers a first portion of an upper insulating layer of the stack and exposes a second portion of the upper insulating layer adjacent to the memory opening, etching the upper insulating layer through the mask to provide a recess in the second portion of the upper insulating layer, and forming a conductive material within the recess to provide a select gate electrode adjacent to the semiconductor channel in the memory opening.