SOI Charging Protection Device Using P+ Substrate Contact
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Solution Overview
Problem
Existing silicon-on-insulator (SOI) semiconductor devices face challenges in protecting against plasma charging damage during fabrication, which affects transistor characteristics and reliability, particularly when connected to non-VSS circuit nodes.
Innovation Solution
The implementation of an SOI film diode and a P+ substrate contact, electrically connecting the drain region, active diode regions, and bulk silicon layer to form a charging protection device, along with shallow trench isolation and conductive contacts, provides effective plasma charging protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional substrate N+ diode is formed to protect plasma process charging, then charging protection is provided, but implementation problems occur due to poor N+ junction diode properties and interaction with substrate properties
Solution Approach 1:
The patent changes the doping type parameter from N+ to P+ for the substrate contact, fundamentally altering the electrical properties of the charging protection structure. This parameter change resolves the implementation problems associated with poor N+ junction diode properties while maintaining the charging protection function.
Solution Approach 2:
Instead of using the conventional N+ substrate diode approach, the patent inverts the doping type to P+, creating a P+ substrate contact that forms a P-N junction with the N-well. This inversion approach eliminates the interaction problems with substrate properties while providing effective charging protection.
2Productivity
If critical feature sizes are reduced to increase package density and signal performance, then chip area and signal propagation delay are improved, but parasitic capacitances of transistors in bulk silicon substrates increase
Solution Approach 1:
The patent segments the substrate into distinct regions with different electrical properties by introducing P+ substrate contacts in N-well regions. This segmentation creates isolated charging protection zones that prevent parasitic capacitance effects from affecting the overall device performance while maintaining high package density.
3Reliability
If an N+ contact is formed in P-doped substrate and connected to SOI device via conductive contacts and metal line, then charging protection is attempted, but a virtual VSS node is created which is higher than VSS causing P+ substrate contact lightning rod approach to fail
Solution Approach 1:
The patent inverts the conventional approach by using P+ substrate contacts instead of N+ contacts. This inversion eliminates the creation of virtual VSS nodes and their associated complexity, providing a simpler and more effective charging protection mechanism that works directly with the P-doped substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces plasma charging damage, improving transistor characteristics such as threshold voltage and latch-up, and enhancing the reliability of SOI devices in advanced technology designs.
Implementation Method 1
undesirable charge damage to components of the SOI device, such as the gate insulation layer may also occur during the course of fabricating such SOI structures. For example, the use of plasma-based etching processes may result in undesirable charge damage
Implementation Method 2
forming an SOI film diode and a P+ substrate contact for charging protection
Data Source
AI summary
Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.