1xN Compiler Routing via Higher-Level Wiring Blockage Avoidance
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Solution Overview
Problem
Current integrated circuit design methodologies face challenges in maintaining physical optimizations and logical coherence throughout the design flow, leading to inefficiencies in power consumption, performance, and area optimization due to the disjointed nature of logic capture and physical realization processes.
Innovation Solution
The implementation of a 1×N compiler that uses higher-level wiring information to determine and avoid blockages in intra-1×N wiring coordinates, enabling a closed-loop design process for routing 1×N building blocks, which maintains physical optimizations and allows for iterative improvements through back-annotation and reassembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual instantiation of gates and manual changes to synthesis flow are used to maintain physical optimizations, then physical optimizations can be maintained, but designers spend considerable time and manual intervention is required
Solution Approach 1:
The system performs self-service by automatically detecting blockages from higher-level wiring and adjusting intra-1×N routing accordingly. The 1×N compiler autonomously examines wiring information, determines blockages, calculates coordinates, and creates routes that avoid blockages without requiring manual designer intervention, thus maintaining physical optimizations while eliminating time-consuming manual updates
Solution Approach 2:
The system implements feedback by using higher-level wiring information to inform intra-1×N routing decisions. The 1×N compiler continuously monitors for blockages created by higher-level wiring and adjusts routing in real-time, creating a closed-loop system where routing decisions are based on current wiring status rather than static pre-determined paths
2Manufacturing precision
If higher-level wiring information is used to determine blockages, then intra-1×N wiring can avoid blockages, but the design process becomes more complex
Solution Approach 1:
The system segments the wiring design process into distinct hierarchical levels: higher-level wiring examination and intra-1×N wiring generation. By separating these functions and processing them at appropriate levels of abstraction, the system achieves precise routing without overwhelming complexity, as each segment handles only its specific portion of the overall wiring task
Solution Approach 2:
The 1×N compiler acts as an intermediary that translates higher-level wiring constraints into intra-1×N routing solutions. Rather than directly managing all wiring details, the compiler mediates between higher-level design decisions and lower-level routing implementation, simplifying the overall process while maintaining precision
3Productivity
If a closed-loop design process is implemented with back-annotation and reassembly, then physical optimizations are maintained and iterative improvements are enabled, but the system complexity increases
Solution Approach 1:
The closed-loop design process enables continuous improvement by maintaining physical optimizations throughout iterative design cycles. Back-annotation preserves optimization data across iterations, and reassembly reconstructs the design with accumulated improvements, ensuring that useful actions (optimizations) continue rather than being lost between iterations
Solution Approach 2:
The system performs preliminary actions by pre-examining higher-level wiring for potential blockages before intra-1×N routing is finalized. By detecting and accounting for blockages in advance, the system prevents routing conflicts rather than resolving them after the fact, improving overall design efficiency
Data Source
AI summary
Embodiments that route 1×N building blocks using higher-level wiring information for a 1×N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1×N building block, determining intra-1×N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates. Further embodiments comprise an apparatus having a higher-level wiring examiner to examine higher-level wiring of an area near a 1×N building block of a physical design representation. The apparatus may also have a blockage determiner to determine a blockage that affects intra-1×N wiring for the 1×N building block and a coordinate calculator to calculate coordinates of a shape of the blockage, wherein the calculated coordinates may enable a routing tool to avoid the shape when creating intra-1×N wiring for the 1×N building block.