Computer Aided Design TRIZ Cases
- Multi-Corner Static Timing Analysis Using Samples-Based Infrastructure
Simultaneous multi-corner static timing analysis using samples-based infrastructure to generate timing reports efficiently.
- Pre-defined Interconnect Wiring for IC Layout Quality
Pre-defined intercell wiring options within cell libraries constrain automated routing tools to select from optimized candidate paths.
- Circuit Partitioning for Large RC Network Current Analysis
Partition circuits into non-linear and linear subcircuits to reduce matrix factorizations, lowering computational costs for large RC networks.
- Lossless Circuit Layout Patches for Deep Learning Verification
Segmenting layouts into fixed-size patches eliminates padding artifacts that obscure design features, enabling accurate machine learning analysis.
- Metal Routing Techniques for Memory Signal Resistance
Extends metal lines with conductive stubs to lower signal resistance, resolving performance degradation from high wire resistance in lower-level memory layers.
- Variable Spacing Interconnect Routing for IC Noise and Electromigration
Automatic routing adjusts track spacing based on current density to enhance noise immunity in integrated circuits.
- FinFET Dummy Fin Insertion for Photoresist Uniformity
Expanded dummy fin cells fill empty IC layout regions, preventing photoresist unevenness and focus issues during photolithography.
- Context-Aware Signal Delay Adjustment for IC Timing Accuracy
Assigns alignment contexts to standard cells to adjust signal delay times based on physical placement relationships.
- Gradient AOCV Tables for IC Timing Closure
k-Level Gradient AOCV tables reduce pessimism in graph-based analysis by applying depth-dependent derates, minimizing area and power consumption.
- Critical Dimension Prediction via Simulated Intensity Curve-Fitting
A computer-programmed method computes critical dimension predictors by curve-fitting simulated intensities across layout features.
- Programmable Logic Circuit Reconfiguration for Information Processing
A processor reconfigures a programmable logic circuit while executing software modules to initiate hardware processing.
- Contact Via Resistance Variability Prediction
A contact via resistance model predicts circuit variability through a novel bucketization scheme.
- EMI Simulation Accuracy via Power Supply Model
A power supply model with impedance data calculates in-IC current for EMI simulation.
- Automated Polysilicon Feature Alignment in IC Layout Design
An EDA tool aligns polysilicon features across chain sets by computing spacing values for parameterized cells.
- Multi-Fanout Net Routing Resource Limiting
Excluding non-conforming routing resources reduces runtime while maintaining symmetry and solution quality.
- 1xN Compiler Routing via Higher-Level Wiring Blockage Avoidance
A 1xN compiler determines intra-wiring coordinates to avoid blockages detected from higher-level wiring information.
- Electromigration-Aware Width Spacing Pattern Tracks
A design system generates electromigration-correct width spacing pattern tracks by estimating pin sizes and splitting oversized pins before routing.
- Area Efficient Power Switch Cell Bridging Doped Wells
A power switch cell bridges two parallel rows of doped wells to enable compact semiconductor layout integration.
- High Current Interconnect Routing in Congested IC Regions
Search-based pattern routing identifies valid intervals and uses spacetiles to guide multi-strand interconnects across congested electronic circuit regions.
- High Speed Channel Modeling via Segmented Layout Analysis
A method segments high speed channel design information into distinct layouts for connection wirings and through electrodes to enable accurate integrated modeling.
- Symbolic Circuit Simulation Using MTBDDs for Analog Nodes
Multi-terminal binary decision graphs model variable channel resistances to enable fast verification of digital circuits containing analog devices.
- Logic Synthesis Using Variable Fan-In Majority Gates
A CAD tool optimizes logic synthesis using variable fan-in majority gates to reduce gate counts and logic depth.
- Radial Bump Pattern Generation for Semiconductor Packaging
A radial bump pattern generation method determines precomputed parameters and creates rings of bump instances oriented perpendicular to a common center line.
- Object-Oriented Circuit Autorouter for Complex Constraint Handling
An object-oriented circuit autorouter manages routing nets using a modular constraint-driven architecture.