Canonical Hierarchical Models for IC Capacitance Extraction
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Solution Overview
Problem
Current methods for capacitance extraction in integrated circuit design, particularly with advanced technologies featuring trench contacts and multi-gate devices, face challenges due to complex conductor geometries and context-dependent characteristics, leading to insufficient speed and accuracy in large-scale designs.
Innovation Solution
The development of canonical hierarchical models that capture capacitance in integrated circuits, including device, hybrid, and interconnect models, enables efficient and accurate capacitance extraction by decomposing complex scenarios into manageable components and applying superposition, scaling, or substitution operations to combine capacitance data from these models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional capacitance extraction methods are used for advanced device technologies with complex conductor geometries, then the extraction process can be performed with simple models, but the accuracy of capacitance extraction deteriorates significantly
Solution Approach 1:
The patent segments the complex capacitance extraction problem into multiple hierarchical levels: device-level canonical models for individual devices, interconnect-level models for conductor groups, and system-level models for the complete circuit. This segmentation allows each level to be modeled with appropriate complexity, improving overall accuracy without overwhelming computational burden.
Solution Approach 2:
The patent introduces canonical models as intermediary representations between the physical device structures and the capacitance extraction process. These canonical models serve as mediators that capture the essential electrical characteristics of complex geometries (like FinFETs and trench contacts) in a standardized form, enabling accurate extraction without requiring complex geometry-specific calculations for each instance.
2Measurement precision
If detailed canonical hierarchical models are created to capture complex device geometries, then capacitance extraction accuracy improves from 25.8% to 1.7%, but the computational complexity and model creation effort increases
Solution Approach 1:
The patent creates universal canonical models that can represent multiple device types and geometries through parameterization. A single interconnect canonical model structure can represent different conductor configurations by adjusting parameters, eliminating the need to create unique complex models for each geometry type while maintaining high extraction accuracy.
Solution Approach 2:
The patent uses parameter changes to adapt canonical models to specific device geometries. By modifying geometric parameters (dimensions, spacing, materials) within the standardized model framework, the same model structure accurately represents various device configurations, reducing model creation complexity while preserving accuracy.
3Productivity
If conventional capacitance extraction methods are used for large-scale integrated circuit designs, then the extraction process is faster with simpler models, but the accuracy becomes insufficient for advanced technologies
Solution Approach 1:
The hierarchical segmentation of the extraction process allows computationally intensive accurate modeling to be applied only where necessary (device-level canonical models for complex structures), while simpler models are used for routine interconnect extraction. This selective application of complexity maintains productivity while improving accuracy for critical regions.
Solution Approach 2:
The patent performs preliminary characterization to create the canonical models before the actual capacitance extraction process. This preliminary action captures the complex geometric effects in advance, allowing the main extraction process to use these pre-computed models for rapid and accurate results, achieving both speed and accuracy.
Data Source
AI summary
A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model to capture a first capacitance of a device having a plurality of first conductors and a second type canonical model to capture a second capacitance between at least a portion of the device and one or more second conductors of the integrated circuit. The method further includes determining a capacitance for the layout based on the applying.