Area Efficient Power Switch Cell Bridging Doped Wells
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Solution Overview
Problem
Integrated circuit layout designers face challenges in reducing component size or increasing functionality without increasing size, due to the required P/N spacing tolerance between power switch cells and standard cells, which constrains the area utilization of power switch cells.
Innovation Solution
A method for generating an area-efficient power switch cell that bridges two parallel rows of doped wells, allowing the power switch cell to be placed such that no P/N spacing tolerance is required, enabling efficient use of the cell boundary area by positioning the standard cell adjacent to the power switch cell with complementary logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the power switch cell is positioned adjacent to standard cells with complementary logic, then area efficiency is improved, but P/N spacing tolerance constraints worsen the area utilization
Solution Approach 1:
The patent merges the power switch cell with the doped well structure by positioning the power switch cell to bridge two parallel rows of doped wells. This merging eliminates the need for separate P/N spacing tolerance between the power switch cell and adjacent standard cells, as the power switch cell directly interfaces with the doped wells. The result is improved area efficiency while maintaining electrical isolation through the doped well structure.
Solution Approach 2:
The doped wells serve as an intermediary structure between the power switch cell and the substrate. By positioning the power switch cell to bridge two parallel rows of doped wells, the doped wells act as mediators that provide electrical isolation and define the boundaries of the power switch cell, thereby eliminating the need for additional P/N spacing tolerance while maintaining proper electrical isolation.
2Adaptability or versatility
If the power switch cell height is increased to accommodate more logic, then functionality is improved, but the cell size increases
Solution Approach 1:
The patent changes the dimensional approach by positioning the power switch cell to bridge two parallel rows of doped wells vertically, rather than expanding horizontally. This allows the power switch cell to accommodate more logic in the vertical dimension by spanning multiple well rows, thereby improving functionality without proportionally increasing the overall cell footprint in the horizontal plane.
Data Source
AI summary
A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.