Lossless Circuit Layout Patches for Deep Learning Verification
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Solution Overview
Problem
Current deep learning applications in physical design verification face challenges due to the inability to efficiently process large and complex circuit layouts, as existing methods either fail to maintain the fidelity of design features or require padding that obscures details and increases data processing needs.
Innovation Solution
A system that uses a pattern library to generate lossless representations of circuit layout portions as tensors, allowing for adaptive sizing without padding, enabling effective analysis by machine learning models while maintaining design fidelity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If padding is used to normalize the size of circuit layout representations, then the size uniformity is improved, but the detail fidelity deteriorates because padding obscures original design features
Solution Approach 1:
The patent segments the circuit layout into multiple fixed-size patches or tiles, each representing a local region. This segmentation allows the model to process layouts of varying overall sizes by breaking them into uniform components, eliminating the need for padding while preserving all original design features within each patch.
Solution Approach 2:
The patent transforms the variable-size 2D layout representation into a structured sequence by introducing a spatial dimension through patch indexing and coordinate encoding. Each patch is accompanied by metadata indicating its position in the original layout, allowing the model to reconstruct the full layout structure without adding padding artifacts.
2Reliability
If the entire circuit layout is processed in a single pass, then the analysis completeness is improved, but the computational complexity increases due to the sheer number of features
Solution Approach 1:
The patent divides the large-scale circuit layout into smaller, manageable patches that can be processed independently and in parallel. This segmentation reduces the computational burden on each processing unit while maintaining overall analysis completeness through aggregation of patch-level results.
Solution Approach 2:
The patent merges the results from multiple patch-level analyses by aggregating features, predictions, or embeddings across all patches. This combining process reconstructs the global layout analysis from local patch analyses, achieving comprehensive coverage without requiring the entire layout to be processed as a single monolithic unit.
3Productivity
If smaller representations of portions of the circuit layout are generated, then the processing efficiency is improved, but the representation fidelity deteriorates due to differing sizes
Solution Approach 1:
The patent segments the circuit layout into fixed-size patches, ensuring each representation has uniform dimensions. This segmentation enables efficient processing while maintaining fidelity because each patch captures complete local design features without being truncated or distorted by variable sizing.
Solution Approach 2:
The patent changes the parameter of representation size from variable to fixed by enforcing uniform patch dimensions. This parameter change enables the use of fixed-size neural network layers and optimizers while preserving all essential design information within each patch, thereby maintaining fidelity despite the reduced scale.
Data Source
AI summary
Embodiments of the invention provide a system, media, and method for deep learning applications in physical design verification. Generally, the approach includes maintaining a pattern library for use in training machine learning model(s). The pattern library being generated adaptively and supplemented with new patterns after review of new patterns. In some embodiments, multiple types of information may be included in the pattern library, including validation data, and parameter and anchoring data used to generate the patterns. In some embodiments, the machine learning processes are combined with traditional design rule analysis. The patterns being generated and adapted using a lossless process that encodes the information of a corresponding area of a circuit layout.