Transistor Gate Shifting for Power Staple Avoidance in IC Routing
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Solution Overview
Problem
The existence of power staples in integrated circuits poses challenges for routing and pin accessibility, necessitating a solution to avoid alignment with cell pins during routing operations.
Innovation Solution
By shifting one or more transistor gates in each row of the integrated circuit and partitioning the circuit row into segments based on fixed objects, the alignment of cell pins and power staples can be avoided, facilitating effective routing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power staples are inserted in integrated circuits, then power delivery is improved, but routing accessibility and pin accessibility deteriorate due to alignment conflicts
Solution Approach 1:
The patent applies dynamics by making the transistor gates movable rather than fixed. The gate positions are dynamically adjusted within allowable ranges to avoid alignment conflicts with power staples, enabling the routing tool to find valid paths without modifying the power staple locations themselves
Solution Approach 2:
The patent segments the circuit rows by identifying fixed objects (such as I/O blocks, macro cells, or other immovable structures) that define boundaries. Transistor gates are then shifted only within segments between these fixed objects, constraining the search space and making the routing problem more manageable while still avoiding power staple conflicts
2Productivity
If transistor gates are shifted to avoid power staple alignment, then routing congestion is reduced, but device layout complexity increases
Solution Approach 1:
The patent performs preliminary action by pre-calculating and storing the minimum and maximum gate positions for each transistor gate before the actual routing process. This pre-computation of gate position ranges eliminates the need for complex real-time calculations during routing, reducing layout complexity while maintaining routing efficiency
Solution Approach 2:
The patent changes parameters by adjusting gate positions within pre-determined minimum and maximum bounds. Rather than allowing arbitrary position changes, the system modifies the position parameter within constrained ranges, simplifying the optimization problem and reducing layout complexity while still achieving congestion reduction
Data Source
AI summary
Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.