Pre-defined Interconnect Wiring for IC Layout Quality
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Solution Overview
Problem
Automated routing tools in integrated circuit design often create suboptimal wire layouts, leading to 'ugly shapes' that increase manufacturing complexity, reduce yield, and introduce lithography hotspots, particularly in lower metal layers like metal-1 layers.
Innovation Solution
Pre-defining candidate intercell wiring options within cell libraries, such as candidate vias, border terminal wires, and inner terminal wires, limits the router's ability to create new connections within cell boundaries, forcing it to use only predefined wires, thereby reducing the occurrence of suboptimal wire layouts and lithography hotspots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If automated routing tools are used to create wire layouts, then routing efficiency and automation are improved, but wire layout quality deteriorates creating ugly shapes and lithography hotspots
Solution Approach 1:
The patent pre-defines candidate wire layouts, via placements, and routing paths within standard cell libraries before the actual routing process. These pre-defined structures are optimized to avoid ugly shapes and lithography hotspots. During routing, the automated tool selects from these pre-defined candidates rather than creating wires from scratch, thus maintaining both automation efficiency and manufacturing precision.
Solution Approach 2:
The patent changes the parameter space by pre-defining discrete candidate options for wire layouts, widths, and routing paths. Instead of continuous optimization that may produce suboptimal results, the system transforms the problem into selecting from a finite set of pre-optimized parameters, ensuring manufacturing quality while maintaining routing automation.
2Area of stationary object
If routers use minimum width wires to achieve dense packing, then area utilization is improved, but manufacturing yield deteriorates due to increased sensitivity to defect induced opens
Solution Approach 1:
The patent changes the wire width parameter by pre-defining multiple candidate widths for different routing scenarios. Instead of uniformly using minimum width, the system selects from pre-determined width options that balance density and reliability. Thicker wires are pre-defined for critical paths and lower metal layers where manufacturing defects are more problematic.
Solution Approach 2:
The patent applies local quality by allowing different wire widths and spacing in different regions of the circuit. Pre-defined candidate structures enable locally optimized wire dimensions based on specific routing needs, layer characteristics, and defect sensitivity, rather than applying a uniform minimum width throughout the entire design.
3Area of stationary object
If routers place wires at minimum separation distances to achieve high density, then routing density is improved, but manufacturing yield deteriorates due to increased sensitivity to defect induced bridges
Solution Approach 1:
The patent changes the wire spacing parameter by pre-defining multiple candidate separation distances. Instead of always using minimum spacing, the system selects from pre-determined spacing options that balance density with manufacturing robustness. Larger spacing is pre-defined for wires that are more susceptible to bridge defects.
Solution Approach 2:
The patent applies local quality by enabling different wire spacing in different locations based on pre-defined candidates. Critical wiring regions with higher defect sensitivity receive larger pre-defined spacing, while less critical regions can use minimum spacing to maintain density. This local optimization resolves the contradiction between overall density and local reliability.
4Adaptability or versatility
If routers create complex wire shapes to connect terminals, then routing flexibility is improved, but manufacturing complexity increases creating lithography hotspots
Solution Approach 1:
The patent pre-defines candidate wire shapes, routing paths, and via placements that are optimized to avoid complex and problematic geometries. During routing, the automated tool selects from these pre-defined simple shapes rather than creating complex paths on the fly. This maintains routing flexibility through multiple pre-planned options while ensuring manufacturing simplicity.
Solution Approach 2:
The patent segments the routing problem into discrete pre-defined candidate paths and structures. Instead of creating continuous complex wire shapes, the system uses segmented pre-defined routing segments that connect terminals through simple, manufacturable paths. This segmentation reduces wire shape complexity while maintaining routing adaptability through selection among multiple segmented options.
Data Source
AI summary
A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or more terminals, and defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal. The method further includes arranging selected cells from the cell library to form a desired layout of an integrated circuit, and routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells.