Automated Polysilicon Feature Alignment in IC Layout Design

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In integrated circuit design, aligning polysilicon features across different chain sets is challenging, requiring manual intervention and being time-consuming, especially in ensuring proper spacing and alignment for fabrication compliance.

Innovation Solution

A method and system that automatically aligns polysilicon features by determining suitable spacing values for pcell instances, allowing for the generation of updated pcell instances with properly aligned poly features, utilizing an Electronic Design Automation (EDA) system with user input and automated processes to adjust poly feature positions and spacing parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If manual alignment of polysilicon features is performed, then alignment precision can be controlled, but design time and manual effort increase significantly

Engineering Contradiction:
Improvepolysilicon feature alignment precisionVSAvoiddesign time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The system automatically performs the alignment operation without requiring manual intervention. The EDA tool computes optimal spacing values and generates updated pcell instances with properly aligned poly features autonomously, allowing the system to serve itself rather than requiring designer intervention for routine alignment tasks.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The invention changes the spacing parameter of polysilicon features automatically. By computing optimal spacing values based on design rules and generating updated pcell instances with modified geometric dimensions, the system transforms manual alignment into an automated parameter adjustment process that maintains precision while reducing time.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If automated alignment process is implemented, then design time is reduced, but complexity of the EDA system increases

Engineering Contradiction:
Improvedesign throughputVSAvoidEDA system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The EDA tool integrates multiple functions into a unified alignment system. The same automated process handles spacing computation, pcell instance generation, and geometric structure updates, making the system multi-functional rather than requiring separate specialized tools for each operation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The pcell parameterization system acts as an intermediary between the alignment computation and the final geometric generation. By using parameterized cell definitions as an intermediate representation, the system simplifies the complexity management - the parameters serve as a bridge that translates alignment requirements into concrete geometric structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If dummy poly features are inserted to enhance critical dimensions, then fabrication compliance is improved, but layout complexity increases

Engineering Contradiction:
Improvefabrication complianceVSAvoidlayout complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system performs preliminary computation of optimal spacing values and pre-generates updated pcell instances with properly aligned poly features before final layout generation. This preliminary action ensures fabrication compliance is built into the design from the start, avoiding the need for complex post-processing adjustments.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8719754B1System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters
Publication Date: 2014.05.06 CADENCE DESIGN SYST INC
  • US8719754B1 patent drawing
  • US8719754B1 patent drawing
  • US8719754B1 patent drawing

AI summary

A method is provided to align poly features within chain sets in an integrated circuit layout design stored in a non-transitory computer readable storage device comprising: vertically aligning a first poly feature of a first pcell instance in a first chain set with a second poly feature of a second pcell instance in a second chain set; configuring a computer to, starting with the aligned first and second poly features, successively determine multiple changed poly feature spacing values associated with at least one of the first and second pcell instances to align successive poly features in chain order in a first horizontal direction; and assigning respective determined changed poly feature spacing values to their associated first or second pcell instances.