High Current Interconnect Routing in Congested IC Regions

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Solution Overview

Problem

Conventional methods for routing high current carrying interconnects in integrated circuits face challenges, particularly in congested regions with blockages, as they fail to find viable solutions and do not employ search-based or area-based strategies effectively.

Innovation Solution

The implementation of high current carrying interconnects using a search-based pattern route strategy, which identifies available areas and determines routing topologies based on pin characteristics, and employs spacetiles to guide the routing engine, allowing for parallel strands of interconnects and various topologies like L-routing, Z-routing, and straight-routing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional routing methods are used for high current carrying interconnects, then routing simplicity is maintained, but routing success rate deteriorates in congested regions with blockages

Engineering Contradiction:

Improverouting success rateVSAvoidrouting method complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by identifying available areas and determining routing topologies before actual routing execution. The system analyzes pin characteristics, identifies valid intervals, and determines feasible routing paths in advance, which significantly improves routing success rate in congested regions while managing complexity through structured preprocessing

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces spacetiles as intermediary elements that guide the routing engine through congested regions. These spacetiles act as mediators between the routing requirements and physical constraints, enabling the system to navigate around blockages effectively while maintaining routing success

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If search-based pattern route strategy is implemented, then routing capability in congested regions improves, but computational complexity increases

Engineering Contradiction:

Improverouting capabilityVSAvoidcomputational complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the routing problem into distinct phases: identifying available areas, determining routing topologies, identifying valid intervals, and executing pattern-based routing. This segmentation allows the system to apply search-based strategies selectively to critical sub-problems, improving overall routing capability while managing computational complexity through divide-and-conquer

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes routing parameters dynamically based on region characteristics. In congested regions with blockages, the system activates search-based pattern routing with specific topologies (L-routing, Z-routing, straight-routing). In less congested areas, simpler routing methods are used, optimizing the balance between routing capability and computational complexity

Inventive Principle:

Principle #35Parameter changes

3Reliability

If wider interconnects are used to carry high current, then current density control improves, but routing flexibility deteriorates due to blockages

Engineering Contradiction:

Improvecurrent density controlVSAvoidrouting flexibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent resolves the conflict between wide interconnect requirements and routing flexibility by utilizing multiple routing layers (dimensionality). The system can route wide interconnects across different metal layers, using vertical vias to transition between layers, thereby maintaining current density control while navigating around blockages in congested regions

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The system performs preliminary analysis to identify available areas and valid intervals for wide interconnect routing before execution. By pre-processing the layout to determine feasible regions for wide traces, the system ensures current density requirements are met while planning routes that avoid blockages, maintaining both reliability and flexibility

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9183343B1Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs

Publication Date: 2015.11.10 CADENCE DESIGN SYST INC

AI summary

Various embodiments implement high current carrying multi-strands of interconnects between two pins in a region of interest within an electronic circuit by performing area-based searches for viable routing solutions using valid intervals. Certain pins that are within a predetermined proximity to each other may be optionally clustered to form a single, wide pin. The region of interest may be first processed to form one or more sets of spacetiles, or the geometries in the region of interest may be projected onto a boundary of the region of interest, to determine the valid interval(s) on along the boundary. The valid intervals may then be used by a router to implement the multi-strands of interconnects. The router also considers the physical, electrical, and manufacturing requirement(s) in implementing the multi-strands of interconnects.