HDL Core Reuse via Synchronization Data Compilation
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Solution Overview
Problem
The time-consuming compile phase in HDL simulation of integrated circuits is a significant bottleneck due to the large size of modern cores and the need for significant computational resources, leading to inefficiencies in the design cycle.
Innovation Solution
A method and system for simulating HDL designs by reusing compiled core units and generating new compiled testbenches using synchronization data, allowing for per-core compilation and reducing the administrative burden and computational resources required, thereby speeding up the simulation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire HDL design is recompiled whenever a core is added or changed, then the simulation maintains accuracy and reliability, but the compilation time and computational resources increase significantly
Solution Approach 1:
The patent segments the HDL design into separate compilable units: testbench code and core code. The testbench is compiled separately from the cores, allowing the testbench to be recompiled without forcing recompilation of all cores. This segmentation enables selective compilation, maintaining simulation accuracy while reducing overall compilation time by only compiling what has changed.
Solution Approach 2:
The patent performs preliminary compilation of cores during a first compilation phase and stores the compiled core units. During subsequent compilations, these pre-compiled core units are reused if unchanged, eliminating the need to recompile them. This preliminary action stores compiled artifacts that can be cached and reused, significantly reducing compilation time in iterative design cycles while maintaining reliability through version tracking.
2Reliability
If all cores are recompiled in each design iteration, then the simulation results remain consistent and reliable, but the computational resources and processing power required increase
Solution Approach 1:
The patent applies local quality by treating different parts of the HDL design with different compilation strategies. Cores that have not changed maintain their compiled state and are reused, while only the testbench and changed cores are recompiled. This localized approach to compilation quality ensures consistency where needed while conserving computational resources in unchanged areas.
Solution Approach 2:
The patent discards the approach of recompiling all cores and recovers computational resources by reusing previously compiled core units. The system tracks which cores have changed and only recompiles those, recovering the computational resources that would otherwise be wasted on recompiling unchanged cores, while maintaining simulation consistency through proper change tracking.
3Productivity
If the compilation process is simplified to reuse cores without separate testbench compilation, then the process becomes faster and easier, but the ability to maintain proper synchronization and signal integrity across core boundaries deteriorates
Solution Approach 1:
The patent segments the compilation process into distinct phases: core compilation and testbench compilation. The testbench compilation phase specifically handles signal synchronization and interface definitions between the testbench and cores. This segmentation allows rapid core reuse while maintaining precise signal synchronization through dedicated testbench compilation that generates appropriate interface code.
Solution Approach 2:
The patent introduces an intermediary compilation phase that processes the testbench and generates synchronization code. This intermediary step translates testbench requirements into proper signal interfaces for reused cores, ensuring signal integrity and synchronization without requiring full recompilation. The intermediary testbench compilation acts as a mediator between the user's testbench changes and the reused core units.
Data Source
AI summary
Simulating a hardware description language design including a core and a testbench can include performing, using a processor, a first compilation of the hardware description language design by generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data describing signals crossing a compile checkpoint boundary. A subsequent compilation of the hardware description language design can be performed by reusing the compiled core unit from the first compilation and generating a new compiled testbench for the testbench using the synchronization data.