High Speed Channel Modeling via Segmented Layout Analysis
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Solution Overview
Problem
Current methods for modeling high-speed channels in semiconductor packages, particularly in 2.5D and 3D ICs with TSVs and metal wirings, face challenges in accuracy and computational efficiency, as conventional modeling schemes struggle to accurately represent the coupling between through electrodes and the semiconductor substrate, especially at GHz frequencies.
Innovation Solution
The method combines a parameter extraction scheme using an on-chip tool with a full wave 3D electromagnetic scheme using an off-chip tool, allowing for accurate modeling of high-speed channels by dividing design information into layouts for connection wirings and through electrodes, and using different modeling schemes and tools for each, thereby reducing calculation complexity while maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single conventional modeling scheme is used for the entire high-speed channel, then the modeling process is simple, but the accuracy of representing coupling between through electrodes and substrate is insufficient
Solution Approach 1:
The high-speed channel is divided into multiple segments: through electrodes, metal wirings, and semiconductor substrate. Each segment is modeled separately using appropriate modeling schemes (full-wave 3D EM for through electrodes, extracted models for metal wirings, and simplified models for substrate), then integrated to form the complete channel model. This segmentation enables accurate representation of coupling effects while managing computational complexity.
2Measurement precision
If a full wave 3D electromagnetic scheme is used for the entire high-speed channel, then the modeling accuracy is improved, but the computational resources and time required increase significantly
Solution Approach 1:
The modeling approach segments the high-speed channel into regions requiring different levels of analysis. Full-wave 3D electromagnetic simulation is applied only to critical regions (through electrodes and immediate surroundings), while other regions use simplified extracted models. This reduces the overall computational domain and time while maintaining accuracy where it matters most.
Solution Approach 2:
Different modeling schemes are applied to different parts of the channel based on their specific characteristics and importance. The full-wave 3D EM scheme is used locally for through electrodes where coupling effects are most significant, while metal wirings and substrate use extracted or simplified models. This localized approach optimizes computational resources while preserving accuracy in critical areas.
3Measurement precision
If detailed modeling of all components is performed, then the accuracy is improved, but the device complexity and computational resources required increase
Solution Approach 1:
The channel components are segmented and modeled with appropriate detail levels. Through electrodes receive detailed full-wave 3D EM modeling, metal wirings use extracted models with relevant parameters, and substrate is modeled with simplified approaches. This selective detail level maintains overall accuracy while reducing the complexity of individual modeling schemes.
Solution Approach 2:
The patent merges multiple modeling results (full-wave 3D EM, extracted models, and simplified models) into a single integrated high-speed channel model. This combination allows each component to be modeled with appropriate detail while the integrated model provides comprehensive accuracy without requiring every component to be modeled at maximum detail.
Data Source
AI summary
A method of modeling a high speed channel in a semiconductor package, the high speed channel including a plurality of first connection wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate, includes: receiving design information of the high speed channel, dividing the design information into a first layout including the plurality of first connection wirings and a second layout including the plurality of through electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout; and obtaining an integrated modeling result of an entirety of the high speed channel by combining results of the first and second modeling operations.