Dynamic Standard Cell Pin Allocation for Routability
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Solution Overview
Problem
Conventional standard cell synthesis techniques face challenges in accurately and efficiently estimating the routability of complex standard cells, especially at advanced technology nodes with fewer than five routing tracks, and lack scalability for large and complex designs.
Innovation Solution
The use of a trained lattice graph routability model to predict routability metrics for local areas and global net connections, influencing transistor placement, and dynamic external pin allocation during routing, integrated with simulated annealing and genetic algorithms to optimize transistor placement and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential standard cell synthesis is used to generate transistor placement and routing, then the approach can handle simple designs, but it is inefficient or incapable of generating routable cell layouts with less than five routing tracks and lacks scalability for large and complex standard cells
Solution Approach 1:
The patent applies preliminary action by performing dynamic external pin allocation during the routing phase rather than fixing pins during placement. The system predicts routability metrics using a trained lattice graph model and uses these predictions to dynamically adjust external pin assignments, enabling the router to optimize routing paths before finalizing the layout. This preliminary routing-aware pin allocation improves routability for complex cells with fewer than five routing tracks while maintaining efficiency through the predictive model.
2Reliability
If simultaneous transistor placement and routing using SMT is performed, then more efficient routing solutions are generated, but scalability is reduced for large and complex standard cells
Solution Approach 1:
The patent applies segmentation by dividing the standard cell synthesis process into distinct phases: placement using simulated annealing, followed by routing with dynamic pin allocation. The lattice graph routability model segments the routing problem into predictable metrics that can be evaluated independently. This segmentation allows the system to handle large and complex standard cells by processing them in manageable stages rather than attempting simultaneous optimization, thereby improving scalability while maintaining routing efficiency through the predictive routing model.
3Ease of manufacture
If conventional standard cell synthesis techniques are used, then the process is simpler, but the ability to estimate routability of complex cells accurately and efficiently is lost
Solution Approach 1:
The patent introduces an intermediary component: the trained lattice graph routability model. This model acts as a mediator between the simple sequential synthesis process and accurate routability estimation. The model takes transistor placement as input and predicts routability metrics without requiring complex simultaneous optimization. This intermediary enables accurate routability estimation while maintaining the simplicity of the sequential synthesis approach, as the model provides predictive guidance without adding significant computational complexity to the overall process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach generates standard cell layouts with improved routability and efficiency, capable of handling complex designs at advanced technology nodes, while minimizing design rule violations and optimizing area, wirelength, and routability.
Implementation Method 1
integrated with simulated annealing and genetic algorithms to optimize transistor placement and routing
Implementation Method 2
integrated with simulated annealing and genetic algorithms to optimize transistor placement and routing
Data Source
AI summary
Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during routing of the nets for the circuit, a graph comprising virtual nodes and edges from the virtual nodes to grid locations for pins external to the circuit is generated. Routing to the external net of the circuit is performed according to the graph nodes and the graph edges.