Violation Ranking for Root Cause Analysis
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Solution Overview
Problem
The complexity of modern electronic device design and manufacturing leads to extensive static verification reports with millions of violations, making it challenging for designers to efficiently analyze and prioritize design errors, often resulting in the suppression of actual design bugs due to the sheer volume of data and time constraints.
Innovation Solution
A computer-implemented method that ranks and orders violations by design objects and attributes, identifying violation hot spots to focus on critical issues, allowing designers to visualize and analyze common root causes efficiently, and apply waivers effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static verification tools are used to test designs against specifications, then design verification is performed, but the volume of violations increases to millions, making analysis time-consuming and tedious
Solution Approach 1:
The patent segments violations into categories (e.g., design errors, process violations) and organizes them by design objects and attributes. This segmentation allows designers to focus on specific areas of interest rather than reviewing all millions of violations uniformly, thereby reducing analysis time while maintaining verification reliability.
Solution Approach 2:
The patent applies local quality by prioritizing and highlighting specific violations based on their severity, frequency, and impact on design objects. By assigning different weights and priorities to different types of violations, the system enables designers to concentrate their attention on the most critical issues, reducing overall analysis time without compromising the detection of important design bugs.
2Productivity
If designers selectively analyze violations based on severity and importance, then analysis efficiency improves, but the risk of suppressing actual design bugs increases
Solution Approach 1:
The patent implements feedback mechanisms that continuously monitor and report on violation patterns, design object health, and attribute distributions. This feedback allows the system to dynamically adjust priority levels and provide real-time insights, ensuring that designers receive timely alerts about potential design bugs while maintaining efficient analysis through automated prioritization.
Solution Approach 2:
The patent introduces an intermediary layer of analysis that automatically processes and prioritizes violations before they reach the designer. This intermediary system acts as a filter and translator, converting raw violation data into prioritized, context-enriched information that guides designer attention to the most critical issues, thereby maintaining both efficiency and reliability.
3Ease of operation
If violation reports are organized by design objects and attributes, then a design-centric view is achieved, but computational complexity increases
Solution Approach 1:
The patent performs preliminary action by pre-processing and organizing violation data into a structured format grouped by design objects and attributes before the designer needs to analyze it. This pre-organization reduces the computational burden during actual analysis, as the data is already sorted and indexed, enabling efficient retrieval and presentation of information from a design-centric perspective.
Solution Approach 2:
The patent applies parameter changes by transforming the violation data representation into a normalized format that emphasizes design objects and attributes as key parameters. By changing the organizational parameters of the data structure, the system achieves a design-centric view that is easier to operate while controlling computational complexity through efficient data structures and indexing techniques.
Data Source
AI summary
Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage. The result is greater efficiency of design violation identification and resolution.