Logic Synthesis Using Variable Fan-In Majority Gates
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Solution Overview
Problem
Current logic optimization and synthesis methods using CMOS logic gates or algorithms with 3-input majority gates result in suboptimal performance and power, performance, and area (PPA) efficiency, particularly when applied to technologies beyond CMOS, and fail to effectively minimize inverters due to limitations in gate count and logic depth optimization.
Innovation Solution
A computer-aided design (CAD) tool that optimizes power, performance, and area (PPA) by using a mix of CMOS gates and majority/minority logic gates with various fan-in and fan-out, employing techniques like MIG synthesis, inverter minimization, and heuristic pattern matching to reduce gate counts and logic depth, while allowing for both single and multiple fan-in M-gates and incorporating ferroelectric capacitors for improved efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 3-input majority gates are used for logic synthesis, then gate count is reduced compared to CMOS gates, but power, performance, and area efficiency deteriorates when applied to technologies beyond CMOS
Solution Approach 1:
The patent extends the logic synthesis approach from fixed 3-input majority gates to variable fan-in majority gates (k-input where k≥3). This parameter change allows the same majority gate primitive to be adapted for different technology nodes and applications, improving PPA efficiency for beyond CMOS technologies while maintaining gate count reduction benefits
Solution Approach 2:
The patent creates a universal logic synthesis methodology that works for both CMOS and beyond CMOS technologies by using majority gates as a technology-agnostic primitive. The approach can be applied across different fabrication technologies, making the solution universally applicable rather than CMOS-specific
2Ease of manufacture
If MIG synthesis initializes from AND-OR-INVERT graphs, then synthesis is possible using majority gates, but suboptimal results occur when final fabrication gates could be majority/minority gates rather than AND/OR/NAND/NOR gates
Solution Approach 1:
Instead of converting AND-OR-INVERT graphs to majority gate implementations, the patent inverts the approach by directly synthesizing from truth tables using majority gates as the fundamental primitive. This eliminates the suboptimal intermediate representation and directly targets the target gate library, achieving optimal gate counts when majority/minority gates are the fabrication gates
3Device complexity
If M-gates are limited to 3 inputs, then synthesis is simpler, but improvement in power, performance, and area relative to static CMOS gates is limited
Solution Approach 1:
The patent changes the fixed parameter of 3 inputs to a variable fan-in parameter k, where k≥3. This allows optimization of the input count based on specific application requirements and technology characteristics, enabling better PPA improvements while maintaining manageable synthesis complexity through systematic algorithms
4Device complexity
If additional M-gates are introduced to reduce inverter count, then inverter minimization is achieved, but logic optimization performance deteriorates due to heuristic limitations
Solution Approach 1:
The patent incorporates feedback mechanisms where the synthesis process iteratively evaluates the impact of adding M-gates for inverter minimization while monitoring overall logic optimization metrics. This feedback loop ensures that inverter reduction does not degrade overall logic optimization performance, allowing simultaneous optimization of multiple objectives
Data Source
AI summary
A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.