Contact Via Resistance Variability Prediction
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Solution Overview
Problem
Current semiconductor circuit designs face significant variability in contact via resistance, particularly in 45 nm CMOS technology, due to layout proximity effects and limited room for contact size increase, leading to trade-offs between contact opens and shorts, and inadequate modeling of resistance distributions.
Innovation Solution
A novel CA resistance model and algorithm incorporating a bucketization scheme to predict and manage contact via resistance variability, accounting for lithographic processing conditions, stud dimensions, and material properties, separating random and systematic effects, and providing more accurate circuit behavior modeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CA size is increased to reduce resistance variability, then contact resistance decreases, but device area increases and layout density decreases
Solution Approach 1:
The patent segments the CA resistance variability into multiple independent components (intrinsic resistance, layout proximity effects, material fill variations, dimensional variations) and models each separately. This allows targeted optimization of each component rather than uniformly increasing CA size, thereby reducing resistance variability without proportionally increasing device area.
Solution Approach 2:
The patent changes multiple parameters simultaneously (CA dimensions, material properties, layout configurations, fabrication conditions) and models their combined effects on resistance. By optimizing the combination of parameters rather than single parameter optimization, the patent achieves reduced resistance variability with minimal area penalty.
2Reliability
If CA size is increased to accommodate overlay tolerance, then contact opens are reduced, but PC-CA shorts increase due to limited room
Solution Approach 1:
The patent separates the analysis of contact opens and PC-CA shorts into distinct modeling components. By independently modeling overlay effects, dimensional variations, and material fill variations, the patent can optimize CA design to minimize both types of defects simultaneously rather than facing a trade-off.
Solution Approach 2:
The patent performs comprehensive variability analysis and modeling before final CA design decisions are made. By predicting resistance variability and potential defects through detailed modeling of multiple parameters, the patent enables preliminary optimization of CA dimensions and layout to prevent both opens and shorts before fabrication.
3Device complexity
If present CA resistance distribution models are used, then design simplicity is maintained, but prediction accuracy of resistance variability is insufficient
Solution Approach 1:
The patent divides the complex resistance variability problem into multiple manageable components (intrinsic resistance, layout effects, material variations, dimensional variations). Each component is modeled separately with appropriate complexity, then combined to achieve high overall prediction accuracy while maintaining reasonable design complexity through modular structure.
Solution Approach 2:
The patent introduces multiple parameters to accurately capture resistance variability (material resistivity, CA dimensions, layout distances, overlay shifts) and develops modeling approaches to handle these parameters efficiently. This enables accurate prediction of variability while providing practical design tools through parametric models.
Data Source
AI summary
A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.