Parameterized Diode Algorithm for Antenna Violation Power Reduction
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Solution Overview
Problem
The antenna effect during the fabrication of MOS transistors can lead to gate oxide damage and increased power consumption due to the insertion of diodes to prevent antenna violations.
Innovation Solution
A parameterized IP algorithm is implemented across a chip hierarchy, where parameterized diodes are scaled and enabled only for antenna violations, allowing for dynamic control of diodes based on specific routing and driver characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diodes are inserted to prevent antenna violations during MOS transistor fabrication, then gate oxide damage is protected, but power consumption increases due to parasitic capacitance
Solution Approach 1:
The patent applies local quality by making the diode protection structure conditional and location-specific. Instead of uniformly adding diodes across all gates, the invention selectively places diodes only at gates that violate antenna rules, determined by calculating antenna ratio = cumulative metal area / gate area. This localized approach protects vulnerable gates while avoiding unnecessary parasitic capacitance at non-violating gates, thereby reducing overall power consumption while maintaining gate oxide protection where needed.
Solution Approach 2:
The patent implements dynamics by making the diode structure configurable and adjustable. The diode is designed as a parameterized structure where the antenna ratio can be modified based on routing configurations. This allows the protection mechanism to adapt dynamically - the diode can be enabled or disabled, and its characteristics adjusted, based on the actual antenna violation severity and routing layout, optimizing the balance between protection and power consumption.
2Reliability
If diodes are added to protect against antenna effects, then manufacturing reliability improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the chip into hierarchical levels (gate level, block level, chip level) and evaluating antenna violations at each level independently. The diode protection is segmented and applied only to specific gates that violate antenna rules, rather than adding complexity uniformly across the entire circuit. This segmented approach maintains manufacturing reliability for vulnerable gates while minimizing overall device complexity.
Solution Approach 2:
The patent implements self-service through automated antenna ratio calculation and diode placement. The design tool automatically calculates antenna ratios based on routing configurations, identifies violating gates, and places diodes only where needed. This automation eliminates manual intervention and reduces design complexity, while the diodes themselves are simple standard cells that integrate seamlessly into the existing circuit without adding significant complexity.
3Use of energy by moving object
If parameterized diodes are scaled and enabled only for antenna violations, then power consumption is reduced, but the complexity of the algorithm increases
Solution Approach 1:
The patent applies preliminary action by performing antenna ratio calculation and diode placement decisions during the design phase, before fabrication. The algorithm pre-evaluates all potential antenna violations by calculating cumulative metal areas and gate areas, determines which gates need protection, and places diodes accordingly. This preliminary analysis eliminates the need for complex runtime decisions or post-fabrication adjustments, reducing power consumption while keeping the algorithm manageable through systematic pre-computation.
Solution Approach 2:
The patent implements feedback through iterative antenna ratio calculation and diode placement verification. The algorithm calculates antenna ratios, identifies violations, places diodes, and then re-evaluates to ensure violations are resolved. This feedback loop continues until all antenna rules are satisfied. The feedback mechanism ensures power consumption is minimized by placing diodes only where necessary, while the systematic iterative approach keeps the algorithm complexity controlled through clear convergence criteria.
Data Source
AI summary
Providing a parameterized IP algorithm for power reduction across a chip hierarchy including for each input pin at a chip hierarchy level, determining a parameterized diode value only for an indication of an antenna violation, wherein a parameterized diode is scaled to protect a gate; and enabling the parameterized diode with the parameterized diode value. Providing a parameterized IP algorithm also includes placing a placeholder parameterized diode for each input pin; for each IP, converting the IP into a parameterized IP; and upon a determination of no antenna violation, disabling the parameterized diode.