FinFET Dummy Fin Insertion for Photoresist Uniformity
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Solution Overview
Problem
The presence of empty regions near fin arrays in integrated circuits (ICs) can lead to uneven photoresist layers during photolithography, causing focus issues and process failures in the formation of other features over fin arrays, which is detrimental to the manufacturing of FinFETs.
Innovation Solution
The insertion of dummy fins in empty regions to create an even topography for the photoresist layer, with the use of expanded dummy fin cells that are derived from standard dummy fin cells by multiplying their dimensions, ensuring minimal interference with the fin array and maintaining design rule density limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If empty regions are left near fin arrays in IC layout, then the layout file size is reduced and manufacturing is simpler, but the photoresist layer becomes uneven causing focus issues and process failures
Solution Approach 1:
Dummy fins are inserted into empty regions during the layout design phase, before photolithography and other manufacturing processes. This preliminary action creates a uniform topography that prevents photoresist layer unevenness and focus issues in subsequent processing steps.
Solution Approach 2:
Standard dummy fin cell designs are copied and placed into empty regions near fin arrays. These copied dummy fin structures replicate the topography of active fins without requiring functional circuitry, thereby uniformizing the photoresist layer while maintaining layout simplicity.
2Reliability
If dummy fins are inserted in empty regions to create even topography, then photoresist layer uniformity is improved, but the layout complexity and file size increase
Solution Approach 1:
The layout is segmented into standard dummy fin cell units that can be systematically placed in empty regions. This segmentation allows for modular insertion of dummy fins, improving process reliability while keeping the layout manageable through standardized repeating elements.
Solution Approach 2:
The dimensions and spacing of dummy fin cells are optimized to balance topography uniformity with file size constraints. By adjusting parameters such as dummy fin width, length, and spacing, the layout achieves sufficient photoresist uniformity while minimizing the quantity of dummy structures required.
3Ease of manufacture
If standard dummy fin cells are used to fill empty regions, then the insertion process is simplified, but the empty regions may not be fully minimized
Solution Approach 1:
Standard dummy fin cell designs are extended in the vertical dimension to create expanded dummy fin cells. This dimensional extension allows dummy fins to reach into adjacent empty regions more effectively, minimizing empty space while maintaining the simplicity of using standardized cell templates.
Solution Approach 2:
Expanded dummy fin cells are designed with asymmetric dimensions that allow them to optimally fill irregular empty regions. By varying the dimensions of dummy fin cells in different orientations and locations, the layout achieves more complete empty region minimization while still using systematic insertion methods.
Data Source
AI summary
A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.