Multi-Threshold Voltage Cell Swapping for Leakage Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern integrated circuit designs face challenges in efficiently balancing timing and leakage power constraints, as existing EDA tools prioritize timing over area and power, leading to increased leakage power issues with scaling technologies below 100-nm feature size.
Innovation Solution
A method is introduced that calculates efficiency values for equivalent cells to swap high-Vt cells with low-Vt cells along timing paths, minimizing leakage current while meeting timing specifications, using an iterative process to optimize the mix of multi-threshold voltage cells without restructuring logic, and limiting swaps to multi-Vt equivalents to preserve design integrity and reduce runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing EDA tools prioritize timing constraints in synthesis, then timing reliability is improved, but leakage power increases
Solution Approach 1:
The patent applies parameter changes by systematically varying the threshold voltage parameter of standard cells along timing paths. It calculates efficiency values for each cell based on timing impact and leakage reduction, then swaps cells to optimize the mix of high-Vt and low-Vt cells. This resolves the contradiction by finding the optimal parameter configuration that balances timing reliability and leakage power.
Solution Approach 2:
The patent applies local quality by making different parts of the circuit have different threshold voltage characteristics. Instead of using uniform cells throughout, it selectively assigns high-Vt cells to non-critical paths and low-Vt cells to critical timing paths, creating a non-uniform quality distribution that optimizes both timing and power locally.
2Loss of energy
If multi-Vt cell mapping is used to reduce leakage, then leakage power is reduced, but synthesis complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the synthesis process into distinct phases: calculating efficiency values for all equivalent cells, selecting cells based on efficiency criteria, and performing iterative swaps. This segmentation makes the complex multi-Vt mapping problem manageable and systematic, reducing the perceived complexity while achieving leakage reduction.
Solution Approach 2:
The patent applies feedback through an iterative process where efficiency values are calculated, cells are selected and swapped, and the process repeats until optimization converges. This feedback mechanism automatically adjusts the cell mapping based on measured timing and leakage characteristics, simplifying the synthesis complexity through automated optimization.
3Loss of energy
If cell swapping is performed to optimize timing-leakage balance, then leakage power is reduced, but runtime increases
Solution Approach 1:
The patent applies partial action by limiting cell swaps to multi-Vt equivalent cells only, rather than allowing all possible cell replacements. This restriction reduces the search space and runtime while still achieving significant leakage reduction, accepting that not all cells need to be swapped to reach optimal performance.
Solution Approach 2:
The patent applies preliminary action by pre-calculating efficiency values for all equivalent cells before the iterative swapping process begins. This preliminary calculation stores optimization data that guides subsequent cell selections, reducing the runtime needed during iterative swaps while maintaining optimization effectiveness.
Data Source
AI summary
A method for designing an integrated circuit, comprising the steps of (A) calculating an efficiency value for each of a plurality of equivalent cells in the design; and (B) selecting a number of the plurality of equivalent cells based on the efficiency values. The equivalent cells (i) decrease an overall delay of a path to meet a timing specification, and (ii) minimize an increase in overall leakage current.