Electromigration-Aware Width Spacing Pattern Tracks
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Solution Overview
Problem
Existing electronic design approaches fail to incorporate electromigration requirements in width spacing patterns, leading to physically correct but electromigration-violating circuit board tracks, which are only detected during later design validation steps.
Innovation Solution
A computer-implemented method that estimates pin sizes based on current information, splits pins above a threshold, and generates electromigration-aware width-spacing-pattern tracks, ensuring both design rule compliance and electromigration correctness before the routing step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing width spacing patterns are used for routing, then design rule compliance is achieved, but electromigration requirements are not met
Solution Approach 1:
The patent performs preliminary electromigration analysis during the layout stage before routing is completed. By estimating current information and calculating required track widths in advance, the system pre-determines electromigration-compliant track dimensions, ensuring that routing decisions are made with EM requirements already incorporated rather than adding them as a post-processing constraint.
Solution Approach 2:
The patent dynamically adjusts track width parameters based on estimated current information. By modifying the track width parameter according to the magnitude of current flowing through each net, the system creates electromigration-aware routing patterns that adapt to different current requirements, transforming static design rules into dynamic, current-dependent dimensional specifications.
2Reliability
If track width is increased to support high current, then electromigration issues are avoided, but manufacturing complexity increases
Solution Approach 1:
The patent applies different track width specifications to different routing segments based on their current requirements. Rather than uniformly increasing all track widths, the system locally adjusts only those tracks carrying high current, while maintaining standard widths for low-current paths. This localized approach to width modification reduces overall manufacturing complexity while ensuring EM compliance where needed.
Solution Approach 2:
The patent creates a dynamic routing design where track widths are determined by the current information of each net rather than fixed design rules. This dynamic width assignment allows the routing to adapt to actual electrical requirements, optimizing the balance between electromigration protection and manufacturing simplicity by assigning wider tracks only where current demands justify the additional complexity.
3Reliability
If pin size is increased to support current, then electromigration compliance is achieved, but layout density decreases
Solution Approach 1:
The patent segments the pin structure into multiple smaller pins rather than using a single large pin. By dividing the total current-carrying area into multiple parallel pins, the system achieves the required electromigration compliance through collective width while maintaining better layout density. This segmentation allows the pins to be arranged in parallel, reducing the overall area footprint compared to a single wide pin.
Solution Approach 2:
The patent transitions from a single-dimension width approach to a multi-dimensional pin arrangement. Instead of simply increasing pin width in one dimension, the system utilizes multiple pins arranged in different spatial positions, effectively using two or three dimensions to achieve the required current capacity. This dimensional expansion allows for better area utilization while maintaining EM compliance.
Data Source
AI summary
Embodiments included herein are directed towards method for electronic design. Embodiments may include receiving, using at least one processor, a placed layout and one or more electronic design simulation datasets including current information associated with at least one pin. Embodiments may further include estimating a width to support the current information associated with the at least one pin and updating a pin size associated with the at least one pin based upon, at least in part, the estimated width. Embodiments may also include identifying at least one pin that is above a predetermined threshold and splitting the at least one pin that is above the predetermined threshold into a plurality of pins. Embodiments may further include generating one or more width-spacing-pattern tracks for one or more internal nets based upon, at least in part, the updated pin size.