2-Bit FeFET Readout Using Asymmetric Polarization Control
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Solution Overview
Problem
Current memory technologies face challenges in efficiently storing and retrieving multiple data states in a single transistor binary non-volatile memory, particularly in ferroelectric field-effect transistors (FeFETs), where maintaining asymmetric polarization states for 2-bit data storage is complex and requires precise voltage control to avoid bit disturbance during writing, erasing, and reading operations.
Innovation Solution
A 2-bit ferroelectric field-effect transistor (FeFET) design with a ferroelectric layer between the gate and source-drain regions, utilizing asymmetric polarization states and specific voltage configurations to store four possible data states (0,1), (1,0), (1,1), or (0,0), allowing for asymmetric writing, erasing, and reading processes without disturbing the opposite bit, by applying distinct voltage combinations to the gate and source-drain terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If asymmetric polarization states are used to store 2-bit data in a single FeFET, then data storage capacity is improved, but device complexity increases due to precise voltage control requirements
Solution Approach 1:
The patent segments the voltage control process into distinct phases (writing phase with first voltage combination, erasing phase with second voltage combination, reading phase with third voltage combination). Each phase uses specific voltage assignments to gate and source-drain terminals that target only the intended bit while preserving the other bit's state, thereby managing complexity through structured temporal separation of operations
Solution Approach 2:
The patent applies different voltage combinations locally to different terminals (gate vs. source-drain) depending on the operation phase. During writing, a first voltage is applied to gate and second voltage to source-drain; during erasing, third voltage to gate and fourth voltage to source-drain; during reading, fifth voltage to gate and sixth voltage to source-drain. This localized voltage application enables selective manipulation of polarization states in different regions of the device
2Manufacturing precision
If precise voltage combinations are applied to write and erase bits, then data manipulation accuracy is improved, but operation time increases due to multiple voltage switching steps
Solution Approach 1:
The patent employs periodic action by structuring operations into distinct phases (writing, erasing, reading) with specific voltage combinations applied in sequence. Each phase uses predetermined voltage levels that are applied and then switched to the next phase's voltage combination, creating a rhythmic pattern of voltage application that ensures accuracy while managing operation time through efficient transitions
3Quantity of substance
If asymmetric polarization states are maintained for 2-bit storage, then storage density is improved, but reliability decreases due to potential bit disturbance during operations
Solution Approach 1:
The patent applies preliminary anti-action by designing voltage combinations that inherently protect the non-target bit from disturbance. During writing operations, the voltage combination is specifically configured to affect only the intended bit while the other bit's polarization state remains stable. Similarly, during reading operations, the voltage combination is designed to sense the target bit without altering its state or disturbing the other bit, thus preventing reliability issues before they can occur
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable storage and retrieval of multiple data states with reduced bit disturbance, improving the efficiency and accuracy of data manipulation in FeFET memory devices by leveraging the bistable polarization states of the ferroelectric layer and controlled voltage applications.
Implementation Method 1
a ferroelectric layer between the gate and source-drain regions, utilizing asymmetric polarization states
Data Source
AI summary
A method (of reading a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes reading the second bit including: applying a gate sub-threshold voltage to the gate terminal; applying a read voltage to the second S/D terminal; applying a do-not-disturb voltage to the first S/D terminal; and sensing a first current at the second S/D terminal; and wherein the read voltage is lower than the do-not-disturb voltage.